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51. 发明授权

US06293772B1 Containment member for a magnetic-drive centrifugal pump 有权
标题翻译：用于磁驱离心泵的容器
公开(公告)号：US06293772B1
公开(公告)日：2001-09-25
申请号：US09428730
申请日：1999-10-28
申请人： Jeffrey S. Brown , Manfred P. Klein , Scott A. McAloon , Peter E. Phelps
发明人： Jeffrey S. Brown , Manfred P. Klein , Scott A. McAloon , Peter E. Phelps
IPC分类号： F04B1700
CPC分类号： F04D13/026 , F04D13/025
摘要： A containment member for a magnetic-drive centrifugal pump includes a reinforcement member cooperating with an inner layer and an outer layer to form a unitary body. The inner layer has a first side defining a generally annular recess and a second side opposite the first side. The second side defines a pocket located coaxially and radially inward with respect to the annular recess. The reinforcement member has a stem portion nested within the pocket. The reinforcement member has a curved portion extending radially outward from the stem portion. The stem portion has a first radial dimension and the curved portion has a second radial dimension greater than the first radial dimension. The outer layer covers the curved portion and is affixed to the curved portion and the inner layer.
摘要翻译：用于磁驱动离心泵的容纳构件包括与内层和外层协作以形成整体的加强构件。内层具有限定大致环形凹部的第一侧和与第一侧相对的第二侧。第二侧限定了相对于环形凹部同轴且径向向内定位的口袋。加强构件具有嵌套在口袋内的柄部。加强构件具有从杆部向径向外侧延伸的弯曲部。杆部分具有第一径向尺寸，并且弯曲部分具有大于第一径向尺寸的第二径向尺寸。外层覆盖弯曲部分并且固定到弯曲部分和内层。

52. 发明授权

US06264440B1 Centrifugal pump having an axial thrust balancing system 有权
标题翻译：具有轴向推力平衡系统的离心泵
公开(公告)号：US06264440B1
公开(公告)日：2001-07-24
申请号：US09428731
申请日：1999-10-28
申请人： Manfred P. Klein , Jeffrey S. Brown , Scott A. McAloon , Peter E. Phelps
发明人： Manfred P. Klein , Jeffrey S. Brown , Scott A. McAloon , Peter E. Phelps
IPC分类号： F04B1700
CPC分类号： F04D29/047 , F04D13/025 , F04D13/026 , F04D29/0413 , F04D29/0416 , F04D29/0465 , F04D29/061
摘要： In accordance with a preferred embodiment of the invention, a centrifugal pump includes a housing having a housing cavity, an inlet, and an outlet. A shaft is located in the housing cavity. A radial bearing coaxially surrounds the shaft. The shaft and the radial bearing are rotatable with respect to one another. The impeller includes an impeller hub within an opening and an impeller recess for receiving the radial bearing. A thrust balancing valve is associated with the impeller hub to define a variable orifice for fluidic communication with the inlet. A wall for containing the pumped fluid has an interior surface with different elevations for inhibiting rotational flow and reducing angular velocity of the fluid. The interior surface is disposed adjacent to a rear portion of the impeller.
摘要翻译：根据本发明的优选实施例，离心泵包括具有壳体腔，入口和出口的壳体。轴位于壳体腔中。径向轴承同轴地围绕轴。轴和径向轴承可相对于彼此旋转。叶轮包括在开口内的叶轮毂和用于容纳径向轴承的叶轮凹部。推力平衡阀与叶轮毂相关联以限定用于与入口流体连通的可变孔口。用于容纳泵送流体的壁具有不同高度的内表面，用于抑制旋转流动并减小流体的角速度。内表面邻近叶轮的后部设置。

53. 发明授权

US06232163B1 Method of forming a semiconductor diode with depleted polysilicon gate structure 有权
标题翻译：形成具有耗尽的多晶硅栅结构的半导体二极管的方法
公开(公告)号：US06232163B1
公开(公告)日：2001-05-15
申请号：US09362549
申请日：1999-07-28
申请人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
发明人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
IPC分类号： H01L218238
CPC分类号： H01L27/0811 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.
摘要翻译：用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

54. 发明授权

US6097069A Method and structure for increasing the threshold voltage of a corner device 失效
标题翻译：提高拐角装置阈值电压的方法和结构
公开(公告)号：US6097069A
公开(公告)日：2000-08-01
申请号：US102196
申请日：1998-06-22
申请人： Jeffrey S. Brown , Robert J. Gauthier , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier , Steven H. Voldman
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/76 , H01L29/00
CPC分类号： H01L21/28167 , H01L21/8238 , H01L29/42368
摘要： A structure for increasing the threshold voltage of a corner device, particularly for shallow trench isolation having narrow devices. An FET comprises a substrate having a channel formed therein under a gate between spaced source and drain regions. A trench isolation region is formed in the substrate around the transistor and on opposite sides of the channel to isolate the transistor from other devices formed in the substrate, with the trench isolation region forming first and second junction corner devices with opposite sides of the channel. A first dielectric layer is formed under the gate and over the channel of the field effect transistor to form a gate insulator for the transistor. A second corner edge dielectric layer is formed under the gate structure and over the first and second corner devices, such that the corner edge dielectric layer increases the thickness of dielectric over each corner device and thus increases the threshold voltage (Vt) and edge dielectric breakdown and decreases MOSFET corner gate-induced drain leakage.
摘要翻译：一种用于增加角装置的阈值电压的结构，特别是对于具有窄装置的浅沟槽隔离。 FET包括在间隔开的源极和漏极区之间的栅极下方形成有沟道的衬底。沟槽隔离区形成在晶体管周围的衬底和通道的相对侧上，以将晶体管与形成在衬底中的其它器件隔离，其中沟槽隔离区形成具有通道相对侧的第一和第二接合角器件。在场效应晶体管的栅极和沟道之下形成第一介电层，以形成晶体管的栅极绝缘体。在栅极结构之下和第一和第二角部器件之上形成第二角边缘电介质层，使得角部边缘电介质层增加每个拐角器件上的电介质厚度，从而增加阈值电压（Vt）和边缘电介质击穿并降低MOSFET栅极引起的漏极泄漏。

55. 发明授权

US6034388A Depleted polysilicon circuit element and method for producing the same 失效
标题翻译：耗尽多晶硅电路元件及其制造方法
公开(公告)号：US6034388A
公开(公告)日：2000-03-07
申请号：US79846
申请日：1998-05-15
申请人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
IPC分类号： H01L21/334 , H01L21/762 , H01L21/8238 , H01L27/06 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L29/66181 , H01L21/76237 , H01L21/76264 , H01L21/823842 , H01L21/82385 , H01L27/0629 , H01L27/1203 , H01L29/94 , H01L21/76283 , Y10S257/907
摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.
摘要翻译：一种包括半导体衬底的电路元件。第一导电类型的阱区形成在衬底的表面中。在基板上形成电介质膜。在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。栅极导体由多晶硅膜形成。栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。在栅极导体的每一侧上形成多晶硅边缘隔离物。第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

56. 发明授权

US5997264A Shaft for a magnetic-drive centrifugal pump using a plurality of grooves 失效
标题翻译：用于使用多个槽的磁驱离心泵的轴
公开(公告)号：US5997264A
公开(公告)日：1999-12-07
申请号：US844405
申请日：1996-09-28
申请人： Manfred P. Klein , Jeffrey S. Brown
发明人： Manfred P. Klein , Jeffrey S. Brown
IPC分类号： F04D13/02 , F04D29/04 , F04D29/041 , F04D29/043 , F04D29/046 , F04D29/047 , F04D29/06 , F04B17/00 , F04B53/18
CPC分类号： F04D29/047 , F04D13/026 , F04D29/0413 , F04D29/043 , F04D29/0465 , F04D29/061 , F05B2240/60 , F05C2203/0817
摘要： The grooved shaft preferably has one or more axial grooves with semi-elliptical or U-shaped groove cross sections. Flat areas adjoin the axial groove or grooves. The flat areas are tapered tangentially relative to a substantially cylindrical shaft area. The grooved shaft optimally has a front shaft radius and a rear shaft radius. The front shaft radius is smaller than the rear shaft radius such that the front shaft radius may be oriented near an impeller intake to decrease hydraulic flow resistance. In practice, the grooved shaft is incorporated into a magnetic-drive centrifugal pump and the grooves are statically oriented in a position of minimal radial loading.
摘要翻译：带槽轴优选地具有一个或多个具有半椭圆形或U形槽横截面的轴向槽。平面区域与轴向凹槽相邻。平坦区域相对于基本上圆柱形的轴区域是切向锥形的。开槽轴最好具有前轴半径和后轴半径。前轴半径小于后轴半径，使得前轴半径可以靠近叶轮进气定向，以降低液压阻力。在实践中，带槽轴被并入磁驱动离心泵中，并且凹槽被静止地定向在最小径向载荷的位置。

57. 发明授权

US5981148A Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby 失效
公开(公告)号：US5981148A
公开(公告)日：1999-11-09
申请号：US895749
申请日：1997-07-17
申请人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , Cuc K. Huynh , Robert K. Leidy , Paul W. Pastel
发明人： Jeffrey S. Brown , James S. Dunn , Steven J. Holmes , Cuc K. Huynh , Robert K. Leidy , Paul W. Pastel
IPC分类号： H01L29/78 , G03F7/095 , G03F7/38 , H01L21/027 , H01L21/265 , H01L21/311 , H01L21/336 , G03C5/56 , H01L21/71
CPC分类号： H01L29/66492 , G03F7/38 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L29/6659 , G03F7/095 , H01L21/26586
摘要： The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

58. 发明申请

US20140039863A1 MODELING SEMICONDUCTOR DEVICE PERFORMANCE 有权
标题翻译：建模半导体器件性能
公开(公告)号：US20140039863A1
公开(公告)日：2014-02-06
申请号：US13562393
申请日：2012-07-31
申请人： Jeffrey S. Brown
发明人： Jeffrey S. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5068 , G06F17/5081
摘要： Disclosed are embodiments for modeling semiconductor device performance using a single compact model despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and despite variations in this dependency across multiple related semiconductor devices due to LLEs. In one embodiment, the actual performance attribute to model parameter dependence of a single semiconductor device is fit to a reference dependence so that changes to the compact model are not required even when changes occur in the performance attribute to model parameter dependency during fitting and/or re-centering. In another embodiment, the actual performance attribute to model parameter dependence of each of multiple related semiconductor devices are fit to a reference dependence so that changes to the compact model are not required even when the performance attribute to model parameter dependency varies across the devices.
摘要翻译：公开了使用单个紧凑型模型来建模半导体器件性能的实施例，尽管由于局部布局效应（LLE）而在拟合和/或重新对中期间发生的单个半导体器件的性能属性与模型参数依赖性的变化，并且尽管在该由于LLE引起的多个相关半导体器件的依赖性。在一个实施例中，单个半导体器件的模型参数依赖性的实际性能属性适合于参考依赖性，使得即使在性能属性中发生改变以在拟合和/或模拟参数依赖性期间发生变化，也不需要对紧凑模型的改变重新定心在另一个实施例中，对于多个相关半导体器件中的每一个的模型参数依赖性的实际性能属性适合于参考依赖性，使得即使当器件的性能属性与模型参数依赖性变化时，也不需要对紧凑模型的改变。

59. 发明授权

US08232819B2 Closed-loop soft error rate sensitivity control 有权
标题翻译：闭环软错误率灵敏度控制
公开(公告)号：US08232819B2
公开(公告)日：2012-07-31
申请号：US12629816
申请日：2009-12-02
申请人： Mark F. Turner , Jeffrey S. Brown
发明人： Mark F. Turner , Jeffrey S. Brown
IPC分类号： H03K19/003
CPC分类号： G11C11/4125 , G11C5/147 , G11C11/41 , G11C29/52 , G11C2029/0409 , G11C2029/5002
摘要： Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.
摘要翻译：公开了一种用于控制由于电子电路上的辐射引起的软错误率（SER）的闭环反馈系统。可变灵敏度软错误率检测器根据软错误率提供和输出。该输出被提供给电压控制。电压控制的输出反馈到传感器的灵敏度控制，从而形成反馈回路。电压控制的输出可以是软错误率传感器的电源。软错误率传感器的输出也可用于启用和禁用容错方案或提醒用户。

60. 发明授权

US08196086B2 Granular channel width for power optimization 有权
标题翻译：颗粒通道宽度进行功率优化
公开(公告)号：US08196086B2
公开(公告)日：2012-06-05
申请号：US12840535
申请日：2010-07-21
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.
摘要翻译：记录具有一个或多个可由计算机读取的单元的单元库的存储介质，并可由计算机用于设计集成电路。一个或多个单元可以具有物理尺寸参数和通道宽度参数。物理尺寸参数可以是一个或多个单元格的占位面积。通道宽度参数可能具有最小驱动程序大小和最大驱动程序大小。通道宽度参数可以定义范围，在该范围内，工具在集成电路的设计流程期间基于一个或多个功率准则改变最大驱动器尺寸和最小驱动器尺寸之间的通道宽度，而不改变占用面积。

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