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51. 发明授权

US06587905B1 Dynamic data bus allocation 失效
标题翻译：动态数据总线分配
公开(公告)号：US06587905B1
公开(公告)日：2003-07-01
申请号：US09606463
申请日：2000-06-29
申请人： Anthony Correale, Jr. , Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Anthony Correale, Jr. , Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged. A corresponding Auxiliary_(read or write) command is routed to the slave units to notify the units when to route normal read or write data to an idle bus. The bus controller may use this added feature to optimize the available bandwidth of independent read and write data busses up to the limit where a read or write bandwidth may be two times that available if the read and write data buses were used only for their normal traffic.
摘要翻译：具有独立读写数据总线的高性能集成电路（IC）使得能够在耦合到总线的器件之间实现全面同时的读和写数据传输。多个主设备和多个从设备使用总线控制器和总线仲裁器的资源进行通信。具有独立且独立仲裁的单独的读写数据总线允许来自不同设备的读取和写入同时发生。许多高性能IC，如片上系统（SOC），具有与中央处理单元（CPU）通信的许多不同功能单元。许多这样的CPU具有在某些应用中可能导致独立总线上的读取和写入流量之间的不平衡的架构。主设备和从设备包含辅助内部读和写数据总线进行复用，使得读或写数据可以互换。相应的辅助（读或写）命令被路由到从单元，以通知单元何时将正常读或写数据传送到空闲总线。总线控制器可以使用这个附加功能来优化独立的读和写数据总线的可用带宽，直到只有在读写数据总线仅用于其正常业务时，读或写带宽可能是可用的两倍。

52. 发明授权

US06430641B1 Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system 有权
标题翻译：可以提高流水线双总线数据处理系统性能的方法，仲裁器和计算机程序产品
公开(公告)号：US06430641B1
公开(公告)日：2002-08-06
申请号：US09304939
申请日：1999-05-04
申请人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： Methods, arbiters, and computer program products determine if a request for an idle bus in a dual bus data processing system is being blocked by one or more pending requests for the other bus. In this circumstance, any such pending request for the other bus is masked by the arbiter so that the request for the idle bus can be granted. Consequently, a more efficient utilization of the dual bus architecture is achieved. In an illustrative embodiment, a bus request is received for a first one of the dual busses. If the address and control busses are unavailable to allow the request to be granted, then an inquiry is made regarding the status of a pending request for the second one of the dual busses that has gained control of the address and control busses. In particular, it is determined whether a primary request has been granted and a secondary request has been pipelined for the second one of the dual busses. If a primary request has been granted and a secondary request has been pipelined, then the priority of the pending requests for the second one of the dual busses are examined. If the priority of the pending requests for the second one of the dual busses are at least as high as the currently pending request for the first one of the dual busses, then these requests are masked so that they no longer appears to be pending, which allows the request for the first one of the dual busses to be granted.
摘要翻译：方法，仲裁器和计算机程序产品确定对双总线数据处理系统中的空闲总线的请求是否被另一总线的一个或多个未决请求阻止。在这种情况下，任何这样的对另一总线的等待请求被仲裁器屏蔽，以便可以授予空闲总线的请求。因此，实现了双总线架构的更有效的利用。在说明性实施例中，为双总线中的第一个接收总线请求。如果地址和控制总线不可用于允许请求被授予，则询问已经获得对地址和控制总线的控制的双总线中的第二个的待决请求的状态。特别地，确定是否已经授权了主要请求，并且为双重总线中的第二个请求已经被流水线化。如果已经批准了主要请求并且已经流水线地执行了次要请求，则检查双总线中第二个请求的优先级。如果对于双总线中的第二个双总线的未决请求的优先级至少等于对于双总线中的第一个双总线的当前未决请求，则这些请求被屏蔽，使得它们不再似乎在等待，其中允许授予第一个双总线的请求。

53. 发明授权

US08850568B2 Method and apparatus for detecting unauthorized access to a computing device and securely communicating information about such unauthorized access 有权
标题翻译：用于检测对计算设备的未授权访问并安全地传达关于这种未授权访问的信息的方法和装置
公开(公告)号：US08850568B2
公开(公告)日：2014-09-30
申请号：US12044409
申请日：2008-03-07
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann
IPC分类号： G06F11/00 , H04L29/06 , G06F21/55
CPC分类号： H04L63/1416 , G06F21/55 , G06F21/554 , G06F2221/2115
摘要： A method and apparatus for detecting attacks against a computing device are described. Such attacks may be detected by the device and reported to a requesting entity in a manner that makes it difficult for an attacker to know that the attack has been detected. Several exemplary embodiments comprising different client/server and client/network type systems are presented.
摘要翻译：描述了用于检测针对计算设备的攻击的方法和装置。这种攻击可以由设备检测并以使得攻击者难以知道已经检测到攻击的方式报告给请求实体。呈现了包括不同客户端/服务器和客户端/网络类型系统的几个示例性实施例。

54. 发明授权

US08839460B2 Method for securely communicating information about the location of a compromised computing device 有权
标题翻译：用于安全地传达关于受损计算设备的位置的信息的方法
公开(公告)号：US08839460B2
公开(公告)日：2014-09-16
申请号：US12208626
申请日：2008-09-11
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann
IPC分类号： G06F11/00 , G06F21/55 , G06F21/88 , G06F21/73 , H04L29/06
CPC分类号： H04L63/1441 , G06F21/55 , G06F21/554 , G06F21/73 , G06F21/88
摘要： A method for securely reporting location information after an attack on a computing device is presented. Such information may be reported to a requesting entity in a manner almost transparent to an attacker. Several exemplary embodiments of systems wherein the method may be used are presented.
摘要翻译：提出了在对计算设备的攻击之后安全地报告位置信息的方法。这样的信息可以以对攻击者几乎透明的方式报告给请求实体。呈现了可以使用该方法的系统的几个示例性实施例。

55. 发明申请

US20120096201A1 Cooperative Writes over the Address Channel of a Bus 有权
标题翻译：总线地址通道上的合作写入
公开(公告)号：US20120096201A1
公开(公告)日：2012-04-19
申请号：US13330734
申请日：2011-12-20
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F13/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.
摘要翻译：公开了一种通过总线进行通信的方法。总线包括写地址通道，写通道和读地址通道。该方法包括经由写入地址信道从发送设备发送地址到接收设备。该方法还包括经由读取地址信道将有效载荷的一部分经由写入通道和有效负载的另一部分同时发送到接收设备。当经由总线同时发送有效负载的多个连续部分时，发送设备被配置为通过经由写入通道发送多个连续部分的第一顺序部分来通过读取地址信道给予写入信道的数据排序偏好，并且发送多个顺序部分的后续顺序部分经由读地址信道。

56. 发明申请

US20110271134A1 Apparatus and Methods Employing Variable Clock Gating Hysteresis for a Communications Port 有权
标题翻译：使用通信端口可变时钟门限滞后的装置和方法
公开(公告)号：US20110271134A1
公开(公告)日：2011-11-03
申请号：US12772484
申请日：2010-05-03
申请人： Richard Gerard Hofmann
发明人： Richard Gerard Hofmann
IPC分类号： G06F1/04
CPC分类号： G06F1/3215 , G06F1/04 , G06F1/3237
摘要： An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.
摘要翻译：一种装置包括通信端口，其被配置为响应于时钟信号而通过总线进行通信，以及时钟信号生成电路，其被配置为产生时钟信号，并且响应于诸如通信事务的控制输入而改变时钟信号的门控迟滞的港口。时钟信号产生电路可以被配置为基于事务的属性（诸如交易的地址和/或交易中传送的有效载荷）来改变时钟信号的选通滞后。

57. 发明申请

US20110004774A1 Temperature Compensating Adaptive Voltage Scalers (AVSs), Systems, and Methods 有权
标题翻译：温度补偿自适应电压调节器（AVS），系统和方法
公开(公告)号：US20110004774A1
公开(公告)日：2011-01-06
申请号：US12701657
申请日：2010-02-08
申请人： David W. Hansquine , Richard Gerard Hofmann , Richard Alan Moore
发明人： David W. Hansquine , Richard Gerard Hofmann , Richard Alan Moore
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.
摘要翻译：自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化条件自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。在一个实施例中，AVS包括数据库。数据库可以配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。数据库允许快速的电压电平决定。在一个实施例中，电压偏移被添加到从数据库检索的电压电平，该电压电平对应于功能电路的目标工作频率。在另一个实施例中，从对应于功能电路的目标工作频率和温度水平的数据库检索电压电平。 AVS可以由参考数据库的基于软件的模块部分或完全控制，以进行电压电平决定。

58. 发明授权

US07822903B2 Single bus command having transfer information for transferring data in a processing system 有权
标题翻译：具有用于在处理系统中传送数据的传送信息的单总线命令
公开(公告)号：US07822903B2
公开(公告)日：2010-10-26
申请号：US11557119
申请日：2006-11-07
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F13/4022
摘要： A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.
摘要翻译：一种用于在处理系统中传送数据的处理系统和方法。处理系统包括总线主控装置，多个从设备和配置成在从设备之间切换总线主控装置的总线互连。每个从设备具有多个地址。总线互连包括DMA控制器，其被配置为响应于来自总线主控装置的单个总线命令，将数据从地址的第一个地址传送到第二个地址。

59. 发明申请

US20100217906A1 Methods And Aparatus For Resource Sharing In A Programmable Interrupt Controller 失效
标题翻译：可编程中断控制器中资源共享的方法与设备
公开(公告)号：US20100217906A1
公开(公告)日：2010-08-26
申请号：US12389413
申请日：2009-02-20
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Michael Egnoah Birenbach
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Michael Egnoah Birenbach
IPC分类号： G06F13/24
CPC分类号： G06F13/26 , Y02D10/14
摘要： Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.
摘要翻译：描述了用于识别活动中断请求以提高性能并降低处理器系统中的功率需求的高效技术。识别有源采样中断请求的方法首先从一组扫描一组采样中断请求，以识别任何扫描组中的活动中断请求。一组中断请求是N个采样中断请求的M / R优先级，M是优先级数，R是资源共享因子。响应于已经识别出用于改善处理高优先级中断请求的等待时间的活动中断请求，组群选择电路被更新为新组。此外，具有活动中断请求的组可以通过早期检测或预期电路来识别。中断请求组的扫描可能会停止，直到达到下一个中断请求采样点以降低功耗。

60. 发明申请

US20090327548A1 Scalable Bus Structure 审中-公开
标题翻译：可扩展总线结构
公开(公告)号：US20090327548A1
公开(公告)日：2009-12-31
申请号：US12551590
申请日：2009-09-01
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/42 , G06F13/14
CPC分类号： G06F13/4265
摘要： A method of communicating over a bus is disclosed and includes transmitting a first data type in a first type field over a first sub-channel of a transmit channel of the bus while concurrently transmitting a second data type in a second type field over a second sub-channel of the transmit channel of the bus. The method also includes receiving data over a receive channel of the bus while transmitting the first data type and the second data type over the transmit channel.
摘要翻译：公开了一种通过总线进行通信的方法，包括在总线的发送信道的第一子信道上在第一类型字段中发送第一数据类型，同时在第二子字段中在第二类型字段中发送第二数据类型 - 总线的发送通道的通道。该方法还包括在通过发送信道发送第一数据类型和第二数据类型的同时在总线的接收信道上接收数据。

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