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51. 发明授权

US06819141B1 High speed, static digital multiplexer 失效
标题翻译：高速静态数字多路复用器
公开(公告)号：US06819141B1
公开(公告)日：2004-11-16
申请号：US09524901
申请日：2000-03-14
申请人： Jieming Qi , Hung Cai Ngo
发明人： Jieming Qi , Hung Cai Ngo
IPC分类号： H03K19094
CPC分类号： H03K17/693
摘要： A high speed static multiplexer comprising: (1) a plurality of data inputs and at least one select input; (2) an output; (3) a high voltage rail and a low voltage rail; (4) a pull-up circuit coupled between the output and the high voltage rail and further coupled to receive the data inputs and the select input so that the pull-up circuit generates a first logic state at the output in response to the selected data input having that first logic state; (5) and a pull-down circuit coupled between the output and the low voltage rail and further coupled to receive the data inputs and the select input, so that the pull-down circuit generates a second logic state at the output in response to the selected data input having that second logic state.
摘要翻译：一种高速静态多路复用器，包括：（1）多个数据输入和至少一个选择输入; （2）输出; （3）高压轨和低压轨; （4）耦合在输出和高电压轨之间的上拉电路，并且还耦合以接收数据输入和选择输入，使得上拉电路响应于所选数据在输出端产生第一逻辑状态具有该第一逻辑状态的输入; （5）和耦合在所述输出和所述低电压轨之间的下拉电路，并且还被耦合以接收所述数据输入和所述选择输入，使得所述下拉电路响应于所述输出和所述选择输入而产生第二逻辑状态所选择的数据输入具有该第二逻辑状态。

52. 发明授权

US06763474B1 System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes 失效
标题翻译：通过使用多级频率合成器来动态调整节点的时钟频率来同步异构计算机系统中的节点的系统
公开(公告)号：US06763474B1
公开(公告)日：2004-07-13
申请号：US09631712
申请日：2000-08-03
申请人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
发明人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
IPC分类号： G06P112
CPC分类号： H03L7/23
摘要： An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.
摘要翻译：用于节点同步的装置和方法，其可以用于系统中的节点不共享公共系统时钟的异构计算机系统中。重要的时间戳附加在交易请求上。时间戳基于“时间”值，其可以简单地是由系统时钟增加的寄存器。由于每个节点都有自己的系统时钟，这些时钟的频率可能会偏移，这会导致时间戳值的变化。如果值漂移太远，数据更新可能会丢失。能够将高分辨率和快速频率调节的频率合成器连接到系统时钟。当检测到主从时间之间的相位偏移时，可以将频率合成器输出改变少量以使两个信号回到相位。

53. 发明授权

US06710668B1 Glitchless wide-range oscillator, and method therefor 失效
标题翻译：无障碍宽范围振荡器及其方法
公开(公告)号：US06710668B1
公开(公告)日：2004-03-23
申请号：US10242256
申请日：2002-09-12
申请人： Gary Dale Carpenter , Hung Cai Ngo , Ivan Vo
发明人： Gary Dale Carpenter , Hung Cai Ngo , Ivan Vo
IPC分类号： H03B520
CPC分类号： H03K3/0315
摘要： According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a “ring”) includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagation delay of m and the N inverters have signal propagation delay of n. The circuitry also includes means for selecting whether to exclude the N inverters from operating in the loop operable for receiving a select signal on a data input. The selecting means times assertion of the select signal on an output to select the number of inverters. In order to glitchlessly change the number of inverters operating in the loop, the selecting means has a certain delay greater than delay n.
摘要翻译：根据本发明的装置形式，用于在环路（也称为“环”）中操作多个逆变器的振荡器电路包括多个逆变器。逆变器包括一系列M个逆变器和一系列N个逆变器。 M个反相器具有m的信号传播延迟，N个反相器具有n的信号传播延迟。电路还包括用于选择是否排除N个反相器在循环中操作以用于接收数据输入上的选择信号的装置。选择装置在输出端上选择选择信号的次数来选择反相器的数量。为了无缝地改变在循环中工作的逆变器的数量，选择装置具有大于延迟n的一定延迟。

54. 发明授权

US06501313B2 Dynamic duty cycle adjuster 有权
公开(公告)号：US06501313B2
公开(公告)日：2002-12-31
申请号：US09749335
申请日：2000-12-27
申请人： David William Boerstler , Daniel Mark Dreps , Byron Lee Krauter , Hung Cai Ngo
发明人： David William Boerstler , Daniel Mark Dreps , Byron Lee Krauter , Hung Cai Ngo
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.

55. 发明授权

US06335900B1 Method and apparatus for selectable wordline boosting in a memory device 失效
标题翻译：用于存储器件中可选字线升压的方法和装置
公开(公告)号：US06335900B1
公开(公告)日：2002-01-01
申请号：US09734226
申请日：2000-12-12
申请人： Ohsang Kwon , Hung Cai Ngo , Kevin John Nowka
发明人： Ohsang Kwon , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： A method and apparatus for selectable word line boosting in a memory device provides operating of the memory device over wide power supply ranges. A voltage reference and a comparator determine whether or not the power supply voltage has dropped below the range in which word line boosting is not required. If the power supply voltage has dropped, word line boosting is enabled, improving the noise margin and access time of the memory when operating at lower voltages.
摘要翻译：用于在存储器件中可选择字线升压的方法和装置提供存储器件在宽电源范围上的操作。电压基准和比较器确定电源电压是否已经下降到不需要字线升压的范围。如果电源电压下降，则启用字线升压，在较低电压下工作时，可提高存储器的噪声容限和存取时间。

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