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51. 发明授权

US06877152B2 Method of inter-field critical dimension control 失效
标题翻译：场间关键尺寸控制方法
公开(公告)号：US06877152B2
公开(公告)日：2005-04-05
申请号：US10402579
申请日：2003-03-28
申请人： Tsai-Sheng Gau , Anthony Yen , Burn J. Lin
发明人： Tsai-Sheng Gau , Anthony Yen , Burn J. Lin
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70625
摘要： A method of inter-field critical dimension control. The method is applied to a wafer with a plurality of dies manufactured by a wafer manufacturing process that includes exposure. According to the method, a plurality of manufacturing modules is obtained by selecting a manufacturing device for each process of the manufacture. Then, for each manufacturing module, exposure is performed with a predetermined exposure energy to obtain critical dimension distribution data corresponding to the predetermined exposure energy, and critical dimension calibration data for each of the dies is further determined. Thus, when one of the manufacturing modules is applied to perform the manufacture, an exposure energy for each of the dies is determined according to the predetermined exposure energy and the critical dimension calibration data for each of the dies, and the manufacture is performed with the exposure energy on each of the dies for the manufacturing module.
摘要翻译：一种场外关键尺寸控制方法。该方法应用于具有通过包括曝光的晶片制造工艺制造的多个模具的晶片。根据该方法，通过选择制造方法的制造装置来获得多个制造模块。然后，对于每个制造模块，以预定的曝光能量进行曝光，以获得对应于预定曝光能量的临界尺寸分布数据，并进一步确定每个模具的临界尺寸校准数据。因此，当应用制造模块之一来执行制造时，根据每个模具的预定曝光能量和临界尺寸校准数据确定每个模具的曝光能量，并且使用用于制造模块的每个模具上的曝光能量。

52. 发明授权

US06620631B1 Plasma etch method for forming patterned layer with enhanced critical dimension (CD) control 有权
标题翻译：用于形成具有增强的临界尺寸（CD）控制的图案层的等离子体蚀刻方法
公开(公告)号：US06620631B1
公开(公告)日：2003-09-16
申请号：US09573807
申请日：2000-05-18
申请人： Hun-Jan Tao , Chia-Shiung Tsai , Anthony Yen
发明人： Hun-Jan Tao , Chia-Shiung Tsai , Anthony Yen
IPC分类号： H01L21302
CPC分类号： H01L22/20 , H01J37/32935
摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a blanket target layer. There is then formed over the blanket target layer a patterned mask layer. There is then measured, while employing an optical method, a linewidth of the patterned mask layer to determine a patterned mask layer measured linewidth. There is then determined a deviation of the patterned mask layer measured linewidth from a patterned mask layer target linewidth. There is then etched, while employing a plasma etch method, the blanket target layer to form a patterned target layer while employing the patterned mask layer as a etch mask layer. Within the method, in conjunction the deviation of the patterned mask layer measured linewidth from the patterned mask layer target linewidth there is adjusted within the plasma etch method at least one plasma etch parameter such that a patterned target layer measured linewidth more closely approximates a patterned target layer target linewidth. Similarly, within the method, the measuring of the patterned mask layer measured linewidth while employing the optical method and the adjusting within the plasma etch method of the at least one plasma etch parameter are undertaken in-situ for each substrate within a series of substrates fabricated while employing the plasma etch method. Within a second embodiment of the present invention a blanket target layer thickness is measured while employing an optical method rather than a patterned masking layer linewidth.
摘要翻译：在微电子制造的制造方法中，首先提供基板。然后在衬底上形成覆盖目标层。然后在毯状目标层上形成图案化的掩模层。然后在采用光学方法时，测量图案化掩模层的线宽以确定图案化掩模层测量的线宽。然后确定图案化掩模层测量的线宽与图案化掩模层目标线宽的偏差。然后在采用等离子体蚀刻方法的同时蚀刻该覆盖层目标层以形成图案化目标层，同时采用图案化掩模层作为蚀刻掩模层。在该方法中，结合图案化掩模层测量的线宽与图案化掩模层目标线宽的偏差，在等离子体蚀刻方法内调节至少一个等离子体蚀刻参数，使得图案化目标层测量的线宽更接近于图案化靶层目标线宽。类似地，在该方法中，在使用光学方法的同时测量线状图案测量线性以及等离子体蚀刻方法内的至少一种等离子体蚀刻参数的调整是在一系列衬底内的每个衬底的原位进行的同时采用等离子体蚀刻方法。在本发明的第二实施例中，使用光学方法而不是图案化掩蔽层线宽来测量覆盖目标层厚度。

53. 发明授权

US06362093B1 Dual damascene method employing sacrificial via fill layer 有权
公开(公告)号：US06362093B1
公开(公告)日：2002-03-26
申请号：US09378459
申请日：1999-08-20
申请人： Syun-Ming Jang , Anthony Yen , Hung-Chang Hsieh
发明人： Syun-Ming Jang , Anthony Yen , Hung-Chang Hsieh
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via. There is then formed into at least a lower portion of the via a sacrificial via fill layer. There is then formed over the patterned second microelectronic layer a patterned second photoresist layer which defines the location of a trench to be formed through the patterned second microelectronic layer, where a first areal dimension of the via is smaller than and contained within a second areal dimension of the trench. There is then etched, while employing a second etch method which employs the second patterned photoresist layer as a second etch mask layer, the patterned second microelectronic layer to form a twice patterned second microelectronic layer which defines the trench, while not completely etching the sacrificial via fill layer within the via to form a no greater than partially etched sacrificial via fill layer within the via. Finally, there is then stripped the no greater than partially etched sacrificial via fill layer from the via to form the reduced height via contiguous with the trench.

54. 发明授权

US06228760B1 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE-OXIDE进行接触或通过照相和氧化物和W化学机械抛光的缺陷还原
公开(公告)号：US06228760B1
公开(公告)日：2001-05-08
申请号：US09263563
申请日：1999-03-08
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介电层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在二电层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

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