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51. 发明授权

US5595926A Method for fabricating a DRAM trench capacitor with recessed pillar 失效
标题翻译：用于制造具有凹柱的DRAM沟槽电容器的方法
公开(公告)号：US5595926A
公开(公告)日：1997-01-21
申请号：US267405
申请日：1994-06-29
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/334 , H01L21/8242 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L28/82 , H01L29/66181
摘要： A method, and resultant structure, is described for fabricating a DRAM trench capacitor with a single pillar recessed below the level of the top surface of the silicon substrate in which it is formed. First and second insulating layers are formed over the silicon substrate, and patterned to form an opening to the silicon substrate. A portion of the silicon substrate is removed in the region defined by the opening, whereby a first trench is formed. Sidewall spacers are formed along the sides of the first trench from a third insulating layer. A first pillar is formed after depositing a first conductive layer between the sidewall spacers and over the trench and removing the first conductive layer except within the first trench. The sidewall spacers are removed. A portion of the silicon substrate in the first trench is removed that is not vertically masked by the pillar, and simultaneously a portion top of the pillar is removed, whereby a second trench and second pillar are formed at a greater depth in the silicon substrate. The remainder of the second insulating layer is also removed. A capacitor dielectric is formed in the second trench over the second pillar. A second conducting layer is formed over the dielectric layer and removed in the region outside of the trench to form the top capacitor electrode.
摘要翻译：描述了一种用于制造DRAM沟槽电容器的方法和结果，该DRAM沟槽电容器具有在其所形成的硅衬底的顶表面的下方凹陷的单个柱体。第一和第二绝缘层形成在硅衬底上，并被图案化以形成到硅衬底的开口。在由开口限定的区域中去除硅衬底的一部分，从而形成第一沟槽。从第三绝缘层沿着第一沟槽的侧面形成侧壁间隔物。在第一导电层沉积在侧壁间隔物之间并在沟槽之上并除去第一沟槽以外的第一导电层时形成第一柱。去除侧壁间隔物。第一沟槽中的硅衬底的一部分被去除而不被柱垂直掩蔽，同时去除柱的一部分顶部，从而在硅衬底中形成更大深度的第二沟槽和第二柱。第二绝缘层的其余部分也被去除。在第二支柱上的第二沟槽中形成电容器电介质。在电介质层上形成第二导电层，并在沟槽外部的区域中去除第二导电层以形成顶部电容器电极。

52. 发明授权

US5587338A Polysilicon contact stud process 失效
标题翻译：多晶硅接触螺母工艺
公开(公告)号：US5587338A
公开(公告)日：1996-12-24
申请号：US428493
申请日：1995-04-27
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76877
摘要： A process for creating a polysilicon contact stud, to connect overlying metallizations, to underlying active device regions in a semiconductor substrate, has been developed. After filling a contact hole with insitu doped polysilicon, and overlying with a titanium film, an anneal cycle is performed to convert the unwanted portions of polysilicon to titanium silicide. The silicide is then selectively removed, leaving polysilicon only in the contact hole, thus resulting in the desired stud configuration.
摘要翻译：已经开发了用于创建多晶硅接触柱以将覆盖的金属化连接到半导体衬底中的底层有源器件区域的工艺。在用原位掺杂多晶硅填充接触孔并且用钛膜覆盖之后，执行退火循环以将多晶硅的不想要部分转化为硅化钛。然后选择性地去除硅化物，仅在接触孔中留下多晶硅，从而产生所需的螺柱结构。

53. 发明授权

US5573967A Method for making dynamic random access memory with fin-type stacked capacitor 失效
标题翻译：具有鳍式叠层电容器的动态随机存取存储器的方法
公开(公告)号：US5573967A
公开(公告)日：1996-11-12
申请号：US811537
申请日：1991-12-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , Y10S438/967
摘要： A method is described for fabricating a DRAM having a fin-type stacked capacitor. The method begins by forming a MOSFET source/drain and gate structure on a silicon substrate. The gate electrode is composed of a first polysilicon layer. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The fin-type stacked capacitors are now formed by depositing a second polysilicon layer over the device and field oxide areas. Alternating layers of polysilicon and insulator are deposited over the device and field oxide areas with the first polysilicon layer being in contact to the device areas for electrical contact and the last polysilicon layer being the topmost of the alternating layers. The stack of alternating polysilicon and insulator layers are now patterned to form the basis of the stacked capacitors. The exposed edges of the insulator layers are controlably and laterally isotropic etched to increase the planned surface area of the capacitor by forming fin-type structures. A fourth polysilicon layer is deposited over the device and field oxide areas to complete the lower electrode of the stacked capacitor. A capacitor dielectric layer is formed over the lower electrode of the capacitor and the top polysilicon electrode is deposited thereover to complete the stacked capacitor.
摘要翻译：描述了一种用于制造具有鳍式叠层电容器的DRAM的方法。该方法开始于在硅衬底上形成MOSFET源极/漏极和栅极结构。栅电极由第一多晶硅层构成。至少部分由氮化硅构成的第一绝缘体层形成在器件和场氧化物区域上。翅片型堆叠电容器现在通过在器件和场氧化物区域上沉积第二多晶硅层而形成。多晶硅和绝缘体的交替层沉积在器件和场氧化物区域上，其中第一多晶硅层与器件区域接触以进行电接触，并且最后的多晶硅层是交替层的最顶层。交替的多晶硅和绝缘体层的堆叠现在被图案化以形成叠层电容器的基础。绝缘体层的暴露边缘可控地和横向各向同性地蚀刻，以通过形成鳍型结构来增加电容器的计划表面积。在器件和场氧化物区域上沉积第四多晶硅层以完成堆叠电容器的下电极。在电容器的下电极上形成电容器电介质层，并且顶部多晶硅电极沉积在其上以完成堆叠的电容器。

54. 发明授权

US5330928A Method for fabricating stacked capacitors with increased capacitance in a DRAM cell 失效
标题翻译：用于在DRAM单元中制造具有增加的电容的叠层电容器的方法
公开(公告)号：US5330928A
公开(公告)日：1994-07-19
申请号：US951794
申请日：1992-09-28
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： A method is described for fabricating a dynamic random access memory having a high capacitance stacked capacitor. Gate structures and associated source/drain structures are formed within the device areas. A first silicon oxide layer is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a thick second polysilicon layer over the device and field oxide areas. Openings are formed to the desired source/drain structures by etching through the second oxide, second polysilicon, and first oxide layers. Cavities are formed between the first and second oxide layers by laterally etching the second polysilicon layer. A third polysilicon layer is deposited over the device and field oxide areas. The second and third polysilicon layers and the first and second oxide layers are patterned so as to have their remaining portions over the planned capacitor areas. The layers are etched leaving the third polysilicon layer as the bottom storage node electrode contacting the source/drain structures. The remaining second and third polysilicon layers form the storage node of the capacitor. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top plate electrode and the contact polysilicon layer and the dielectric layer are patterned to complete the stacked capacitor.
摘要翻译：描述了一种用于制造具有高电容堆叠电容器的动态随机存取存储器的方法。栅极结构和相关的源极/漏极结构形成在器件区域内。在器件和场氧化物区域上形成第一氧化硅层。现在通过首先在器件和场氧化物区域上沉积厚的第二多晶硅层来形成堆叠的电容器。通过蚀刻通过第二氧化物，第二多晶硅和第一氧化物层，将所希望的源极/漏极结构形成开口。通过横向蚀刻第二多晶硅层，在第一和第二氧化物层之间形成空穴。在器件和场氧化物区域上沉积第三多晶硅层。图案化第二和第三多晶硅层以及第一和第二氧化物层，使其剩余部分在规划的电容器区域上。当底部存储节点电极接触源极/漏极结构时，这些层被蚀刻离开第三多晶硅层。剩余的第二和第三多晶硅层形成电容器的存储节点。电容器电介质层形成在底部电极多晶硅层上。沉积接触多晶硅层作为顶板电极，并且对接触多晶硅层和电介质层进行图案化以完成叠层电容器。

55. 发明授权

US5126916A Stacked capacitor dram cell and method of fabricating 失效
标题翻译：堆叠电容器电容器及其制造方法
公开(公告)号：US5126916A
公开(公告)日：1992-06-30
申请号：US810832
申请日：1991-12-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A DRAM having stacked high capacitance capacitors formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the polysilicon layer so as to have portions over the planned stacked capacitor areas, forming a silicon oxide layer on the exposed surface of the polysilicon, removing the silicon oxide layer from horizontal surfaces of the polysilicon layer by anisotropic etching, removing the polysilicon layer by isotropic etching leaving vertical silicon oxide structures, and forming openings to desired source/drain structures of the DRAM using lithography and etching. A bottom electrode polysilicon layer is deposited over the device and field oxide areas to make contact to the source/drain structures. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top storage node electrode and the contact polysilicon layer and the dielectric layers are patterned.
摘要翻译：通过在其上的场氧化物区域上沉积厚的未掺杂的多晶硅层而形成堆叠的高电容电容器的DRAM，对多晶硅层进行构图以便在预定的叠层电容器区域上形成部分，在多晶硅的暴露表面上形成氧化硅层，通过各向异性蚀刻从多晶硅层的水平表面去除氧化硅层，通过各向同性蚀刻去除多晶硅层，留下垂直的氧化硅结构，以及使用光刻和蚀刻在DRAM的所需源极/漏极结构上形成开口。底部电极多晶硅层沉积在器件和场氧化物区域上以与源极/漏极结构接触。电容器电介质层形成在底部电极多晶硅层上。沉积接触多晶硅层作为顶部存储节点电极，并且接触多晶硅层和电介质层被图案化。

56. 发明授权

US08368220B2 Anchored damascene structures 有权
标题翻译：锚定镶嵌结构
公开(公告)号：US08368220B2
公开(公告)日：2013-02-05
申请号：US11252498
申请日：2005-10-18
申请人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
发明人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps.
摘要翻译：埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤。

57. 发明授权

US08034711B2 Bonding structure and fabrication thereof 有权
标题翻译：粘结结构及其制造
公开(公告)号：US08034711B2
公开(公告)日：2011-10-11
申请号：US11964195
申请日：2007-12-26
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L21/76849 , H01L21/76867 , H01L21/76886 , H01L23/53233 , H01L23/5329 , H01L24/03 , H01L24/13 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05147 , H01L2224/05647 , H01L2224/05681 , H01L2224/05684 , H01L2224/13101 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/48647 , H01L2224/48684 , H01L2224/48747 , H01L2224/48784 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/48781 , H01L2224/48681
摘要： A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
摘要翻译：公开了一种接合结构及其制造方法。本发明的接合结构包括形成在绝缘体层中的铜基焊盘和基本上覆盖铜基焊盘顶表面的保护层。保护层是自对准的，其材料选自金属氮化物，铜合金，铜化合物及其组合。

58. 发明申请

US20090155965A1 METHOD OF FABRICATING A NON-FLOATING BODY DEVICE WITH ENHANCED PERFORMANCE 有权
标题翻译：制造具有增强性能的非浮动体装置的方法
公开(公告)号：US20090155965A1
公开(公告)日：2009-06-18
申请号：US12391307
申请日：2009-02-24
申请人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/336 , H01L21/762 , H01L21/76
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region.
摘要翻译：提供了一种方法，其包括在半导体衬底上形成第一半导体层，在第一半导体层上生长第二半导体层，在第一半导体层上形成复合形状，每个复合形状包括上覆氧化物形状和基底第二半导体形状，第一半导体层的部分暴露在复合形状之间，在复合形状的侧面上形成间隔物，在第一半导体层的暴露的顶部形成掩埋的氧化硅区域，并且在第一半导体层的部分位置潜在的第二半导体形状，选择性地去除导致第二半导体形状的耐氧化形状和间隔物，以及形成第二半导体形状的半导体器件，其中半导体器件的第一部分覆盖第一半导体层，并且其中第二部分半导体器件叠加 y是一个埋置的氧化硅区域。

59. 发明授权

US07221584B2 MRAM cell having shared configuration 有权
标题翻译：具有共享配置的MRAM单元
公开(公告)号：US07221584B2
公开(公告)日：2007-05-22
申请号：US11053379
申请日：2005-02-08
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny D. Tang
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny D. Tang
IPC分类号： G11C11/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/228
摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.
摘要翻译：磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

60. 发明申请

US20060163735A1 Damascene process at semiconductor substrate level 有权
标题翻译：半导体衬底级的镶嵌工艺
公开(公告)号：US20060163735A1
公开(公告)日：2006-07-27
申请号：US11357697
申请日：2006-02-17
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.
摘要翻译：半导体衬底级别的镶嵌结构和工艺。在半导体衬底上设置预金属电介质层，该开口露出衬底上的接触区域。在暴露的接触区域上设置有缓冲金属层，在开口的内部设有阻挡层。导体设置在缓冲金属层上，基本上填充开口以电连接到接触区域。

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