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51. 发明授权

US08541862B2 Semiconductor device with self-biased isolation 有权
标题翻译：具有自偏置隔离的半导体器件
公开(公告)号：US08541862B2
公开(公告)日：2013-09-24
申请号：US13307449
申请日：2011-11-30
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/063 , H01L21/761 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/423 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type.
摘要翻译：一种器件包括：具有表面的半导体衬底，具有第一导电类型的半导体衬底中的漏极区，设置有漏极区的半导体衬底中的阱区，具有第一导电类型的阱区，所述半导体衬底中延伸穿过所述阱区，所述掩埋隔离层具有第一导电类型，设置在所述阱区和所述掩埋隔离层之间的还原表面场（RESURF）区，所述RESURF区具有第二导电类型，以及所述半导体衬底中的插塞区域从所述衬底的表面延伸到所述RESURF区域，所述插塞区域具有所述第二导电类型。

52. 发明授权

US07795674B2 Dual gate LDMOS devices 有权
标题翻译：双门LDMOS器件
公开(公告)号：US07795674B2
公开(公告)日：2010-09-14
申请号：US12560588
申请日：2009-09-16
申请人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/66537 , H01L29/66659 , H01L29/7831
摘要： An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.
摘要翻译： N沟道器件的一个实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。横向隔离壁围绕衬底的至少一部分并且与孔间隔开。第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。与第一个门相隔开的第二个栅极覆盖着N阱。与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

53. 发明申请

US20090244928A1 DUAL GATE LATERAL DIFFUSED MOS TRANSISTOR 有权
标题翻译：双门侧向扩散MOS晶体管
公开(公告)号：US20090244928A1
公开(公告)日：2009-10-01
申请号：US12060105
申请日：2008-03-31
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H02M3/335 , H01L27/088 , H01L21/822
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
摘要翻译：适用于可以以超过例如5MHz或更大的开关频率工作的开关模式转换器的公开的功率晶体管包括覆盖在半导体衬底的上表面上的栅极电介质层和覆盖的半导体衬底的第一和第二栅电极栅介质层。第一栅电极横向定位成覆盖在衬底的第一区域上。第一衬底区域具有第一类型的掺杂，其可以是n型或p型。功率晶体管的第二栅电极覆盖栅极电介质，并且横向地位于衬底的第二区域上方。第二衬底区域具有与第一类型不同的第二掺杂类型。晶体管还包括位于衬底内的漂移区域，该漂移区域紧邻衬底的上表面并横向地位于第一和第二衬底区域之间。

54. 发明申请

US20080166849A1 LDMOS device and method 有权
标题翻译： LDMOS设备和方法
公开(公告)号：US20080166849A1
公开(公告)日：2008-07-10
申请号：US11650188
申请日：2007-01-04
申请人： Hongning Yang , Veronique C. Macary , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/7624 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66659 , H01L29/7835
摘要： An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.
摘要翻译：描述了具有非常轻掺杂的衬底（42）的N沟道器件（40,60），其中设置有间隔开的P（46）和N（44）阱，其侧边缘（461,45）延伸到表面（47）。栅极（56）覆盖在P（46）和N（44）孔之间的表面（47）上。与源极（50）相邻的P阱边缘（461）基本上与左边缘边缘（561）对准。所述N阱边缘（45）位于所述右边缘边缘（562）内或所述右边缘边缘（562）中，所述右边缘边缘（562）与所述漏极（48）间隔开第一距离（471）。 N阱（44）期望地包括与漏极（48）欧姆接触的较重的掺杂区域（62），并且其左边缘（621）位于右栅极边缘（562）和漏极（48）之间的大约一半处）。使用门（56）作为掩模，将HALO注入口袋（52）设置在左门边缘（561）下方。所得到的器件（40,60）在较高电压下工作，Rdson较低，HCI较少，非常低的截止状态泄漏。 P和N掺杂剂互换以提供P沟道器件。

55. 发明申请

US20070228506A1 Composite capacitor and method for forming the same 有权
标题翻译：复合电容器及其形成方法
公开(公告)号：US20070228506A1
公开(公告)日：2007-10-04
申请号：US11397493
申请日：2006-04-03
申请人： Won Min , Geno Fallico , Amanda Kroll , Hongning Yang , Jiang-Kai Zuo
发明人： Won Min , Geno Fallico , Amanda Kroll , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/00 , H01G4/30
CPC分类号： H01G4/33 , H01G4/236 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.
摘要翻译：电子组件（98）包括衬底（20），具有形成在衬底上的第一和第二导体（38,54）的电容器，形成在衬底上并且电连接到第一衬底的第一组导电构件（76）电容器的导体，以及形成在衬底上并且电连接到电容器的第二导体的第二组导电构件（78）。

56. 发明授权

US09466665B2 High voltage diode 有权
公开(公告)号：US09466665B2
公开(公告)日：2016-10-11
申请号：US14697195
申请日：2015-04-27
申请人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L23/58 , H01L29/06 , H01L29/861 , H01L29/66 , H01L27/12
CPC分类号： H01L29/063 , H01L27/1207 , H01L29/0692 , H01L29/66204 , H01L29/861
摘要： A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

57. 发明申请

US20160284841A1 Composite Semiconductor Device with Different Channel Widths 有权
标题翻译：具有不同通道宽度的复合半导体器件
公开(公告)号：US20160284841A1
公开(公告)日：2016-09-29
申请号：US14669415
申请日：2015-03-26
申请人： Won Gi Min , Pete Rodriquez , Hongning Yang , Jiang-Kai Zuo
发明人： Won Gi Min , Pete Rodriquez , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7816 , H01L27/0211 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/1095 , H01L29/66681 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构在饱和区域中具有比第二多个晶体管结构中的每个晶体管结构更低的电阻。

58. 发明申请

US20160099341A1 HIGH BREAKDOWN VOLTAGE LDMOS DEVICE 有权
标题翻译：高电压LDMOS器件
公开(公告)号：US20160099341A1
公开(公告)日：2016-04-07
申请号：US14968343
申请日：2015-12-14
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

59. 发明授权

US09306060B1 Semiconductor devices and related fabrication methods 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US09306060B1
公开(公告)日：2016-04-05
申请号：US14548616
申请日：2014-11-20
申请人： Hongning Yang , Daniel J. Blomberg , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/08
CPC分类号： H01L29/7823 , H01L21/26513 , H01L29/0623 , H01L29/0634 , H01L29/0646 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1095 , H01L29/402 , H01L29/66689 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型的半导体材料的主体区域，在体区内具有第二导电类型的半导体材料的源极区域，具有第二导电类型的半导体材料的结隔离区域，漏极区域具有第二导电类型的半导体材料以及具有第二导电类型的半导体材料的第一和第二漂移区。第一漂移区域横向地位于漏极区域和结隔离区域之间，结隔离区域横向位于第一漂移区域和第二漂移区域之间，并且第二漂移区域横向居住在体区域和结隔离区域之间。

60. 发明授权

US09093567B2 Diodes with multiple junctions and fabrication methods therefor 有权
标题翻译：具有多个结的二极管及其制造方法
公开(公告)号：US09093567B2
公开(公告)日：2015-07-28
申请号：US14072151
申请日：2013-11-05
申请人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L23/58 , H01L29/861 , H01L29/66 , H01L21/265
CPC分类号： H01L29/66121 , H01L21/265 , H01L21/26513 , H01L21/32053 , H01L29/0649 , H01L29/08 , H01L29/6609 , H01L29/66128 , H01L29/861 , H01L29/8611
摘要： An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.
摘要翻译：二极管的实施例包括半导体衬底，具有第一导电类型的第一接触区域，与第一接触区域横向隔开的第二接触区域，并具有第二导电类型，设置在半导体衬底中的第一接触区域之间的第一接触区域以及与第一接触区域电连接并且具有第一导电类型的第二接触区域和设置在半导体衬底中的具有第二导电类型并与第二接触区域电连接的掩埋区域。掩埋区域横向延伸穿过第一接触区域和中间区域以分别建立第一和第二接合点。第一结具有比第二结低的击穿电压。

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