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51. 发明授权

US06514850B2 Interface with dielectric layer and method of making 失效
公开(公告)号：US06514850B2
公开(公告)日：2003-02-04
申请号：US09775010
申请日：2001-01-31
申请人： Li-Qun Xia , Huong Thanh Nguyen , Ellie Yieh , Dan Maydan
发明人： Li-Qun Xia , Huong Thanh Nguyen , Ellie Yieh , Dan Maydan
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/02115 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/3105 , H01L21/31116 , H01L21/3144 , H01L21/76801 , H01L21/76807 , H01L21/76826
摘要： Methods of forming an interface in a dielectric material to act as an indicator for terminating an etching process, and products produced thereby.

52. 发明授权

US06511920B2 Optical marker layer for etch endpoint determination 失效
标题翻译：用于蚀刻终点测定的光学标记层
公开(公告)号：US06511920B2
公开(公告)日：2003-01-28
申请号：US09882111
申请日：2001-06-14
申请人： Huong Thanh Nguyen , Yunsang Kim , Ellie Yieh , Li-Qun Xia
发明人： Huong Thanh Nguyen , Yunsang Kim , Ellie Yieh , Li-Qun Xia
IPC分类号： H01L2131
CPC分类号： H01L21/76832 , H01L21/76813 , H01L21/76826 , H01L21/76829 , H01L22/24 , Y10S438/931
摘要： A method of forming an optical marker layer for etch endpoint determination in integrated circuit fabrication processes is disclosed. The optical marker layer is used in conjunction with organic and/or carbon-containing material layers that are used as bulk insulating materials and barrier materials. The optical marker layer is formed on the bulk insulating material layer and/or the barrier material layer by incorporating an optical marker into the surface thereof. The optical marker is incorporated into the surface of the bulk insulating material layer and/or the barrier material layer by treating such layer with an optical marker-containing gas. The optical marker layer provides an optical marker emission spectrum when it is etched during a subsequent patterning step.
摘要翻译：公开了一种在集成电路制造工艺中形成用于蚀刻端点确定的光学标记层的方法。光学标记层与用作体绝缘材料和阻隔材料的有机和/或含碳材料层结合使用。通过在其表面上并入光学标记物，在体绝缘材料层和/或阻挡材料层上形成光学标记层。通过用含有光学标记的气体处理该层，将光学标记物结合到体绝缘材料层和/或阻挡材料层的表面中。当在随后的图案化步骤中蚀刻时，光学标记层提供光学标记发射光谱。

53. 发明授权

US06413583B1 Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound 有权
标题翻译：通过有机硅化合物和羟基形成化合物的反应形成液状二氧化硅层
公开(公告)号：US06413583B1
公开(公告)日：2002-07-02
申请号：US09338470
申请日：1999-06-22
申请人： Farhad K. Moghadam , David W. Cheung , Ellie Yieh , Li-Qun Xia , Wai-Fan Yau , Chi-I Lang , Shin-Puu Jeng , Frederic Gaillard , Shankar Venkataraman , Srinivas Nemani
发明人： Farhad K. Moghadam , David W. Cheung , Ellie Yieh , Li-Qun Xia , Wai-Fan Yau , Chi-I Lang , Shin-Puu Jeng , Frederic Gaillard , Shankar Venkataraman , Srinivas Nemani
IPC分类号： C23C1640
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02203 , H01L21/02208 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L21/02362 , H01L21/31053 , H01L21/3122 , H01L21/31604 , H01L21/31612 , H01L21/76828 , H01L21/76834
摘要： A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre-metal dielectric layers, inter-metal dielectric layers, and shallow trench isolation dielectric layers in sub-micron devices. The hydroxyl compound can be prepared prior to deposition from water or an organic compound. The silicon oxide layers are preferably deposited at a substrate temperature less than about 40° C. onto a liner layer produced from the organosilicon compound to provide gap fill layers having a dielectric constant less than about 3.0.
摘要翻译：一种通过在低于约400℃的衬底温度下通过有机硅化合物和羟基形成化合物的反应沉积低介电常数的氧化硅层的方法。低介电常数膜含有残余碳并可用于间隙填充层，预金属介电层，金属间介电层和亚微米器件中的浅沟槽隔离电介质层。羟基化合物可以在从水或有机化合物沉积之前制备。氧化硅层优选在低于约40℃的衬底温度下沉积到由有机硅化合物制备的衬里层上，以提供介电常数小于约3.0的间隙填充层。

54. 发明授权

US06360685B1 Sub-atmospheric chemical vapor deposition system with dopant bypass 失效
标题翻译：具有掺杂剂旁路的亚大气压化学气相沉积系统
公开(公告)号：US06360685B1
公开(公告)日：2002-03-26
申请号：US09075561
申请日：1998-05-05
申请人： Li-Qun Xia , Ellie Yieh
发明人： Li-Qun Xia , Ellie Yieh
IPC分类号： C23C1600
CPC分类号： H01L21/02129 , C23C16/401 , C23C16/455 , C23C16/52 , H01L21/022 , H01L21/02271 , H01L21/31625
摘要： A sub-atmospheric chemical vapor deposition (“SACVD”) system with a bypass from a dopant source to an exhaust system and related methods and devices. The flow of dopant may be established by dumping the dopant flow directly to the foreline of a vacuum exhaust system of an SACVD system, rather than flowing the dopant through the chamber. Establishing the dopant flow in this manner prior to the deposition of a silicon glass film on a substrate allows the initial portion of the silicon glass film to be doped at a higher level. Prior apparatus resulted in a dopant-deficient region of silicon glass formed before the dopant was fully flowing. In one embodiment, a doped silicon glass film is used as a dopant source for a semiconductor material, in another embodiment, a multi-layer doped silicon glass film achieves superior reflow.
摘要翻译：具有从掺杂剂源到排气系统的旁路的亚大气压化学气相沉积（“SACVD”）系统及相关方法和装置。可以通过将掺杂剂流直接转移到SACVD系统的真空排气系统的前级管线而不是使掺杂剂流过室来建立掺杂剂的流动。在将硅玻璃膜沉积在衬底上之前以这种方式建立掺杂剂流可以使硅玻璃膜的初始部分以更高的水平被掺杂。先前的装置导致在掺杂剂完全流动之前形成的硅玻璃的掺杂剂缺陷区域。在一个实施例中，掺杂硅玻璃膜用作半导体材料的掺杂剂源，在另一个实施方案中，多层掺杂硅玻璃膜实现优异的回流。

55. 发明授权

US06348099B1 Methods and apparatus for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions 有权
标题翻译：在低于大气压和高温条件下沉积金属前介质层的方法和装置
公开(公告)号：US06348099B1
公开(公告)日：2002-02-19
申请号：US09334437
申请日：1999-06-16
申请人： Li-Qun Xia , Ellie Yieh , Srinivas Nemani
发明人： Li-Qun Xia , Ellie Yieh , Srinivas Nemani
IPC分类号： C23C1600
CPC分类号： H01L21/31625 , C23C16/401 , H01L21/02129 , H01L21/02164 , H01L21/02271 , H01L21/02301 , H01L21/02312 , H01L21/02315 , H01L21/0234 , H01L21/02362
摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800° C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
摘要翻译：本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

56. 发明授权

US5862057A Method and apparatus for tuning a process recipe to target dopant concentrations in a doped layer 失效
标题翻译：用于调整处理配方以靶向掺杂层中的掺杂剂浓度的方法和装置
公开(公告)号：US5862057A
公开(公告)日：1999-01-19
申请号：US709436
申请日：1996-09-06
申请人： Li-Qun Xia , Ellie Yieh
发明人： Li-Qun Xia , Ellie Yieh
IPC分类号： H01J37/32 , H01L21/316 , H01L21/66 , G06F17/00
CPC分类号： H01L21/02274 , H01J37/32935 , H01L21/02129 , H01L21/02271 , H01L21/31625 , H01L22/20
摘要： A method and apparatus for tuning a process recipe to target specific dopant concentrations in a doped layer. The present invention controls the process tuning based on predetermined and easily updatable trend curves for that process. The present invention simplifies the tuning process, shortens the time required to tune the process recipe, and is independent of any personal experience, thereby reducing reliance on the variable skills and experience level of any individual equipment support engineer. The present invention uses a computer program based on process characterization to replace the traditional manual tuning approach. Further, the present invention iteratively corrects for process drift and makes possible efficient tuning of dopant concentration levels in the deposited doped film. Other embodiments of the present method and apparatus provide for storage of the tuning history so as to allow incorporation of the history in order to account for the dopant flow drift. Accordingly, the process characterization may be eliminated for a different individual deposition system. The present invention minimizes the number of trials needed before attaining a doped film with the desired dopant concentrations. Additionally, training of equipment support engineers to perform process tuning is made simpler.
摘要翻译：一种用于调整工艺配方以靶向掺杂层中的特定掺杂剂浓度的方法和装置。本发明基于该过程的预定且易于更新的趋势曲线控制过程调整。本发明简化了调整过程，缩短了调整过程配方所需的时间，并且独立于任何个人经验，从而减少了对任何单独设备支持工程师的可变技能和经验水平的依赖。本发明使用基于过程表征的计算机程序来代替传统的手动调谐方法。此外，本发明迭代地校正了工艺漂移，并且使得沉积的掺杂膜中的掺杂剂浓度水平成为可能的有效调谐。本方法和装置的其它实施例提供了调谐历史的存储，以允许并入历史以便考虑掺杂剂流漂移。因此，可以针对不同的个体沉积系统消除过程表征。本发明使获得具有所需掺杂剂浓度的掺杂膜之前所需的试验数目最小化。此外，设备支持工程师进行过程调整的培训更简单。

57. 发明授权

US5812403A Methods and apparatus for cleaning surfaces in a substrate processing system 失效
标题翻译：在基板处理系统中清洁表面的方法和装置
公开(公告)号：US5812403A
公开(公告)日：1998-09-22
申请号：US748095
申请日：1996-11-13
申请人： Gary Fong , Li-Qun Xia , Srinivas Nemani , Ellie Yieh
发明人： Gary Fong , Li-Qun Xia , Srinivas Nemani , Ellie Yieh
IPC分类号： B08B7/00 , C23C16/44 , C23C16/455 , C23C16/511 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/31 , G06F19/00
CPC分类号： C23C16/45512 , B08B7/0035 , C23C16/4404 , C23C16/4405
摘要： The present invention provides a method for cleaning a processing chamber. According to a specific embodiment, the method includes steps of depositing a dielectric film on a wafer on a ceramic heater in the processing chamber in a first time period, with the ceramic heater heated to a first temperature of at least about 500.degree. C. during the deposition step; and introducing reactive species into the processing chamber from a clean gas that is input to a remote microwave plasma system during a second time period, with the ceramic heater heated to a second temperature of at least about 500.degree. C. during the introducing step. The method also includes cleaning surfaces in the processing chamber, with cleaning performed by the reactive species. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
摘要翻译：本发明提供了一种清洁处理室的方法。根据具体实施方式，该方法包括以下步骤：在第一时间段内在处理室中的陶瓷加热器上的晶片上沉积电介质膜，陶瓷加热器在第一温度下加热至少约500℃ 沉积步骤; 以及在第二时间段内从被输入到远程微波等离子体系统的清洁气体将反应物质引入到处理室中，在引入步骤期间陶瓷加热器加热至至少约500℃的第二温度。该方法还包括清洁处理室中的表面，并进行由反应物质进行的清洁。特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

58. 发明授权

US08143174B2 Post-deposition treatment to enhance properties of Si-O-C low K films 失效
标题翻译：后沉积处理以提高Si-O-C低K膜的性能
公开(公告)号：US08143174B2
公开(公告)日：2012-03-27
申请号：US12013232
申请日：2008-01-11
申请人： Li-Qun Xia , Frederic Gaillard , Ellie Yieh , Tian H. Lim
发明人： Li-Qun Xia , Frederic Gaillard , Ellie Yieh , Tian H. Lim
IPC分类号： H01L21/26
CPC分类号： H01L21/02126 , C23C16/0218 , C23C16/401 , C23C16/56 , H01L21/02071 , H01L21/02203 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/02312 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/3146 , H01L21/31604 , H01L21/31612 , H01L21/31633 , H01L21/76807 , H01L21/76826 , H01L21/76837 , Y10S438/931
摘要： A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally takes place in a reducing environment while heating the substrate. The densification treatment is particularly suitable for silicon-oxygen-carbon low dielectric constant films that have been deposited at low temperature.
摘要翻译：一种用于提供具有增强的粘合性和稳定性的电介质膜的方法。该方法包括在还原气氛中使膜致密化的后沉积处理，以提高如果该膜不原位固化的稳定性。致密化通常在还原环境中进行，同时加热基底。致密化处理特别适用于在低温下沉积的硅 - 氧 - 碳低介电常数膜。

59. 发明申请

US20080145998A1 METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE 失效
标题翻译：形成低K双重DAMASCENE互连结构的方法
公开(公告)号：US20080145998A1
公开(公告)日：2008-06-19
申请号：US11531493
申请日：2006-09-13
申请人： GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/76
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

60. 发明授权

US07132369B2 Method of forming a low-K dual damascene interconnect structure 失效
标题翻译：形成低K双镶嵌互连结构的方法
公开(公告)号：US07132369B2
公开(公告)日：2006-11-07
申请号：US10745344
申请日：2003-12-22
申请人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/302
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

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