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51. 发明授权

US08243523B2 Sensing operations in a memory device 有权
标题翻译：在存储设备中检测操作
公开(公告)号：US08243523B2
公开(公告)日：2012-08-14
申请号：US12720239
申请日：2010-03-09
申请人： Jonathan Pabustan , Vishal Sarin , Dzung H. Nguyen
发明人： Jonathan Pabustan , Vishal Sarin , Dzung H. Nguyen
IPC分类号： G11C11/34
CPC分类号： G06F3/0613 , G06F3/0655 , G06F3/0679 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C16/3459
摘要： Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.
摘要翻译：公开了感测方法，编程方法，存储器件和存储器系统。在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。比较确定存储单元的状态。

52. 发明授权

US08223551B2 Soft landing for desired program threshold voltage 有权
标题翻译：软着陆所需的程序阈值电压
公开(公告)号：US08223551B2
公开(公告)日：2012-07-17
申请号：US12389048
申请日：2009-02-19
申请人： Vishal Sarin , Frankie F. Roohparvar , Jung-Sheng Hoei , Jonathan Pabustan
发明人： Vishal Sarin , Frankie F. Roohparvar , Jung-Sheng Hoei , Jonathan Pabustan
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
摘要翻译：公开了编程存储器单元的方法。在至少一个实施例中，通过应用第一组编程脉冲来编程到初始阈值电压，以及施加第二组编程脉冲来编程到最终阈值电压来实现编程。

53. 发明申请

US20120069675A1 REDUCING NOISE IN SEMICONDUCTOR DEVICES 有权
标题翻译：减少半导体器件中的噪声
公开(公告)号：US20120069675A1
公开(公告)日：2012-03-22
申请号：US13308976
申请日：2011-12-01
申请人： Vishal Sarin , Frankie F. Roohparvar , Jung Sheng Hoei
发明人： Vishal Sarin , Frankie F. Roohparvar , Jung Sheng Hoei
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3418
摘要： The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
摘要翻译：本公开包括用于降低半导体器件中的噪声的方法，装置，模块和系统。一个方法实施例包括将复位电压施加到半导体器件的控制栅极一段时间。该方法还包括在施加复位电压之后感测半导体器件的状态。

54. 发明申请

US20120033504A1 ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：在非易失性存储器件中消除电压降低
公开(公告)号：US20120033504A1
公开(公告)日：2012-02-09
申请号：US13276359
申请日：2011-10-19
申请人： Vishal Sarin , Dzung H. Nguyen
发明人： Vishal Sarin , Dzung H. Nguyen
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful.
摘要翻译：在擦除存储器单元的存储块时，包含要擦除的存储块的半导体存储器可以以高的正电压被偏置。构成存储块的存储单元的控制栅极可以用负电压偏置。然后可以执行擦除验证以确定存储器块是否已被成功擦除。如果存储块尚未被擦除，则可以重复以正电压偏置桶和具有负电压的控制栅的擦除操作，直到擦除验证成功。

55. 发明授权

US08111550B2 M+N bit programming and M+L bit read for M bit memory cells 有权
标题翻译：对M位存储单元进行M + N位编程和M + L位读取
公开(公告)号：US08111550B2
公开(公告)日：2012-02-07
申请号：US13005291
申请日：2011-01-12
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C27/005 , G11C2211/5641
摘要： A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
摘要翻译：描述了存储器件和编程和/或读取过程，其以比所需的更高的阈值电压分辨率编程和/或读取存储器阵列中的单元。在编程非易失性存储器单元中，这允许在编程期间更准确的阈值电压放置，并且能够对程序干扰进行预补偿，从而提高单元上随后的任何读取或验证操作的准确性。在读/读存储器单元中，增加的阈值电压分辨率允许更准确地解释存储器单元的编程状态，并且还能够更有效地使用概率数据编码技术，例如卷积码，部分响应最大似然（PRML）密度奇偶校验（LDPC），Turbo和网格调制编码和/或解码，降低了存储器的总体错误率。

56. 发明申请

US20120008399A1 METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES 有权
标题翻译：包括表征记忆细胞信号线的记忆的操作方法
公开(公告)号：US20120008399A1
公开(公告)日：2012-01-12
申请号：US13235995
申请日：2011-09-19
申请人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line.
摘要翻译：操作存储器的方法有助于补偿存储器单元信号线传播延迟，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。方法包括通过确定存储单元信号线的RC时间常数来选择存储器的存储单元信号线并表征存储单元信号线。

57. 发明申请

US20110122717A1 REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES 有权
标题翻译：在外部地址响应中更换记忆细胞的有缺陷的位点
公开(公告)号：US20110122717A1
公开(公告)日：2011-05-26
申请号：US13017168
申请日：2011-01-31
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/04
CPC分类号： G11C29/848
摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.
摘要翻译：提供控制器和存储器件。在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列存储设备。在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列存储单元列的序列的单元，使得无缺陷列替代缺陷列。无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

58. 发明申请

US20110069547A1 SENSING AGAINST A REFERENCE CELL 有权
标题翻译：感染参考细胞
公开(公告)号：US20110069547A1
公开(公告)日：2011-03-24
申请号：US12955419
申请日：2010-11-29
申请人： Frankie F. Roohparvar , Vishal Sarin
发明人： Frankie F. Roohparvar , Vishal Sarin
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/28
摘要： Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.
摘要翻译：公开了存储器件，大容量存储器件和操作存储器的方法，诸如适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的那些。这种存储器件的编程可以包括在表示期望的位模式的范围内对目标阈值电压进行编程。读取这样的存储器件可以包括产生指示目标存储器单元的阈值电压的模拟数据信号。可以相对于参考单元感测目标存储器单元，包括连接到存储器单元的目标串的存储器单元的虚拟串，并且例如通过使用差分放大器来感测参考单元和目标单元之间的差异。这可能允许更广泛的电压范围用于数据状态。

59. 发明授权

US07907444B2 Memory device reference cell programming method and apparatus 有权
标题翻译：存储器件参考单元编程方法和装置
公开(公告)号：US07907444B2
公开(公告)日：2011-03-15
申请号：US12236892
申请日：2008-09-24
申请人： Vishal Sarin , Frankie F. Roohparvar
发明人： Vishal Sarin , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C7/14 , G11C11/5628 , G11C16/0483 , G11C2211/5634
摘要： Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.
摘要翻译：公开了存储器件和方法，例如那些有助于整个存储器单元阵列中的参考单元的分配方案的存储器件和方法。例如，一个这样的分配方案按行交错格式分配参考单元，其中每列包含单个参考单元。还公开了以重复或伪随机模式分配的多个参考小区的附加方案。

60. 发明申请

US20110058413A1 MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：在非易失性存储器件中缓解数据从后向模式和程序干扰的破坏
公开(公告)号：US20110058413A1
公开(公告)日：2011-03-10
申请号：US12912027
申请日：2010-10-26
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26
CPC分类号： G11C16/3418
摘要： In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
摘要翻译：在所公开的实施例之一中，使用写入算法来消除由于存储器单元中的反向图案效应，单元到单元电容耦合和程序干扰引起的错误。要编程的原始数据在存储器单元的初始编程操作之前被调整。然后在另一个编程操作中将原始数据编程到存储器单元中。在替代实施例中，读取调整权重数据值与存储器单元的每个串联串相关联。权重数据值用于补偿在初始字线读取期间读取的数据。在每次读取和读取调整之后更新权重数据值，使得在随后的读取操作中使用经调整的权重数据值。

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