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51. 发明授权

US08448120B2 RC extraction for single patterning spacer technique 有权
标题翻译： RC提取单图案间隔技术
公开(公告)号：US08448120B2
公开(公告)日：2013-05-21
申请号：US13045839
申请日：2011-05-09
申请人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/50 , G03F1/36 , G03F1/38 , G06F17/5081 , G06F2217/84 , H01L27/0207
摘要： A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.
摘要翻译：一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

52. 发明授权

US08327301B2 Routing method for double patterning design 有权
标题翻译：双图案设计的路由方法
公开(公告)号：US08327301B2
公开(公告)日：2012-12-04
申请号：US12616956
申请日：2009-11-12
申请人： Yi-Kan Cheng , Lee-Chung Lu , Ru-Gun Liu , Chih-Ming Lai
发明人： Yi-Kan Cheng , Lee-Chung Lu , Ru-Gun Liu , Chih-Ming Lai
IPC分类号： G06F17/50
CPC分类号： G03F7/70466 , G03F1/00 , G03F7/70433 , G03F7/705 , G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： In a method of designing a double patterning mask set, a chip is first divided into a grid that includes grid cells. A metal layer of the chip is laid out. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first indicator, and all right-boundary patterns of the metal layer are assigned with a second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set. All patterns assigned with the first indicator are transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set.
摘要翻译：在设计双重图案掩模组的方法中，首先将芯片划分成包括网格单元的网格。布置芯片的金属层。在基本上每个网格单元中，金属层的所有左边界图案被分配有第一指示符，并且金属层的所有右边界图案被分配有第二指示符。从一行中的一个网格单元开始，指示符更改在整行中传播。网格单元中的所有图案都转移到双重图案掩模集合。分配有第一指示符的所有图案被转移到双重图案掩模组的第一掩模，并且分配有第二指示符的所有图案被转移到双重图案掩模组的第二掩模。

53. 发明申请

US20120288786A1 RC EXTRACTION FOR SINGLE PATTERNING SPACER TECHNIQUE 有权
标题翻译： RC提取单模式间距技术
公开(公告)号：US20120288786A1
公开(公告)日：2012-11-15
申请号：US13045839
申请日：2011-05-09
申请人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Cheng-I Huang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G03F1/00 , G06F17/50 , G03F7/20
CPC分类号： G06F17/50 , G03F1/36 , G03F1/38 , G06F17/5081 , G06F2217/84 , H01L27/0207
摘要： A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.
摘要翻译：一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

54. 发明授权

US08214773B2 Methods for E-beam direct write lithography 有权
标题翻译：电子束直写光刻方法
公开(公告)号：US08214773B2
公开(公告)日：2012-07-03
申请号：US12617470
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Ru-Gun Liu , Chih-Ming Lai
发明人： Lee-Chung Lu , Yi-Kan Cheng , Ru-Gun Liu , Chih-Ming Lai
IPC分类号： G06F17/50
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/78 , H01J37/3174
摘要： A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system.
摘要翻译：一种形成用于晶片的集成电路的方法包括提供电子束直接写入（EBDW）系统。为晶片生成栅格，其中栅格包括栅格线。为晶片布置了集成电路，其中集成电路中的基本上没有敏感特征跨越电网的栅格线。使用EBDW系统在晶片上执行EBDW。

55. 发明授权

US08201111B2 Table-based DFM for accurate post-layout analysis 有权
标题翻译：基于表的DFM，用于精确的布局后分析
公开(公告)号：US08201111B2
公开(公告)日：2012-06-12
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

56. 发明申请

US20080072191A1 Sanity checker for integrated circuits 有权
标题翻译：集成电路的检查器
公开(公告)号：US20080072191A1
公开(公告)日：2008-03-20
申请号：US11521095
申请日：2006-09-14
申请人： George H. Chang , Yi-Kan Cheng , Chen-Teng Fan , Chen-Lin Yang , Yung-Chin Hou , Chu-Ping James Wang
发明人： George H. Chang , Yi-Kan Cheng , Chen-Teng Fan , Chen-Lin Yang , Yung-Chin Hou , Chu-Ping James Wang
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： This invention discloses a method for sanity checking integrated circuit (IC) designs based on one or more predefined sub-circuits with at least one predefined checking criteria, the method comprising automatically reading one or more netlists, identifying one or more sub-circuits in the netlists isomorphic to at least one of predefined sub-circuits, identifying one or more device parameters for sanity checking the identified sub-circuits, and comparing the identified device parameters against the predefined checking criteria.
摘要翻译：本发明公开了一种基于具有至少一个预定义的检查标准的一个或多个预定义子电路的完整性检查集成电路（IC）设计的方法，所述方法包括自动读取一个或多个网表，识别所述子电路中的一个或多个子电路网表与至少一个预定义的子电路同构，识别一个或多个设备参数，以便确认所识别的子电路，以及将所识别的设备参数与预定义的检查标准进行比较。

57. 发明授权

US09672315B2 Optimization for circuit migration 有权
公开(公告)号：US09672315B2
公开(公告)日：2017-06-06
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

58. 发明授权

US09000524B2 Method and apparatus for modeling multi-terminal MOS device for LVS and PDK 有权
标题翻译：用于建立LVS和PDK的多端MOS器件的方法和装置
公开(公告)号：US09000524B2
公开(公告)日：2015-04-07
申请号：US13081092
申请日：2011-04-06
申请人： Chau-Wen Wei , Cheng-Te Chang , Chin-yuan Huang , Chih Ming Yang , Yi-Kan Cheng
发明人： Chau-Wen Wei , Cheng-Te Chang , Chin-yuan Huang , Chih Ming Yang , Yi-Kan Cheng
IPC分类号： H01L29/66 , H01L27/088 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/02 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5072 , G06F2217/66 , H01L21/823493 , H01L21/823892 , H01L23/528 , H01L27/0207 , H01L27/0629 , H01L27/088 , H01L28/20
摘要： An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device.
摘要翻译：一种装置包括彼此相邻形成的两个n型金属氧化物半导体（MOS）器件。每个n型MOS器件还包括形成在隔离环中的一对面对二极管。对该装置进行建模的方法包括在标准单元库中重新使用四端MOS器件模型，并将四端MOS器件模型和隔离环模型组合成4T MOS加隔离环模型。对该装置进行建模的方法还包括在第一n型MOS器件的体接触和第二n型MOS器件的体接触之间添加伪器件。

59. 发明授权

US08694938B2 Discrete device modeling 有权
标题翻译：离散设备建模
公开(公告)号：US08694938B2
公开(公告)日：2014-04-08
申请号：US13534526
申请日：2012-06-27
申请人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
发明人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.
摘要翻译：除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。可以使用一组RC值将离散器件建模为宏器件。以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

60. 发明申请

US20140007028A1 DISCRETE DEVICE MODELING 有权
标题翻译：离散装置建模
公开(公告)号：US20140007028A1
公开(公告)日：2014-01-02
申请号：US13534526
申请日：2012-06-27
申请人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
发明人： Ching-Shun Yang , Chih Ming Yang , Wei-Yi Hu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.
摘要翻译：除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。可以使用一组RC值将离散器件建模为宏器件。以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

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