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51. 发明申请

US20090170322A1 Method for Manufacturing Semiconductor Device Including Vertical Transistor 审中-公开
标题翻译：包括垂直晶体管的半导体器件制造方法
公开(公告)号：US20090170322A1
公开(公告)日：2009-07-02
申请号：US12164831
申请日：2008-06-30
申请人： Cheol Kyu Bok
发明人： Cheol Kyu Bok
IPC分类号： H01L21/308
CPC分类号： H01L29/66666
摘要： A method for manufacturing a semiconductor device including a vertical transistor comprises: depositing a n-layered (here, n is an integer ranging from 2 to 6) mask film over a semiconductor substrate; forming a photoresist pattern over the n-layered mask film; etching the mask film with the photoresist pattern as an etching mask until the mth layer (here, m=n−1) mask film is exposed to form a trench; filling an insulating film in the trench; removing the mask film of the insulating film to form an insulating film pattern; and patterning the mth layer mask film with the insulating film pattern as an etching mask until the semiconductor substrate is exposed.
摘要翻译：一种用于制造包括垂直晶体管的半导体器件的方法，包括：在半导体衬底上沉积n层（这里，n为2至6的整数）掩模膜; 在n层掩模膜上形成光致抗蚀剂图案; 用光致抗蚀剂图案作为蚀刻掩模蚀刻掩模膜，直到第m层（这里m = n-1）掩模膜暴露以形成沟槽; 在沟槽中填充绝缘膜; 去除绝缘膜的掩模膜以形成绝缘膜图案; 并且利用绝缘膜图案作为蚀刻掩模对第m层掩模膜进行构图，直到暴露出半导体衬底。

52. 发明申请

US20090004604A1 METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20090004604A1
公开(公告)日：2009-01-01
申请号：US11964693
申请日：2007-12-26
申请人： Ki Lyoung LEE , Cheol Kyu Bok
发明人： Ki Lyoung LEE , Cheol Kyu Bok
IPC分类号： G03F7/26
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/0273 , H01L21/0338 , H01L21/31144
摘要： A method for forming a fine pattern of a semiconductor device comprises forming a spin-on-carbon layer over an underlying layer, forming an anti-reflection pattern including a silicon containing polymer with a first etching mask pattern, forming a photoresist pattern including a silicon containing polymer with a second etching mask pattern between elements of the first etching mask pattern, and etching the spin-on-carbon layer with the etching mask patterns to reduce the process steps and the manufacturing cost, thereby obtaining a uniform pattern profile.
摘要翻译：用于形成半导体器件的精细图案的方法包括在下层上形成自旋碳层，用第一蚀刻掩模图形成包含含硅聚合物的抗反射图案，形成包括硅的光致抗蚀剂图案在第一蚀刻掩模图案的元件之间具有第二蚀刻掩模图案，并用蚀刻掩模图案蚀刻自旋碳层，以减少工艺步骤和制造成本，从而获得均匀的图案轮廓。

53. 发明授权

US6087065A Photoresist film for deep ultra violet and method for forming photoresist film pattern using the same 有权
标题翻译：用于深紫外线的光致抗蚀剂膜和使用其形成光致抗蚀剂膜图案的方法
公开(公告)号：US6087065A
公开(公告)日：2000-07-11
申请号：US222808
申请日：1998-12-29
申请人： Cha Won Koh , Cheol Kyu Bok
发明人： Cha Won Koh , Cheol Kyu Bok
IPC分类号： G03F7/004 , C08F8/30 , C08F220/02 , C08F220/58 , C08L33/24 , G03F7/039 , G03F7/26 , H01L21/027 , G03F7/30
CPC分类号： G03F7/039 , C08F220/58 , C08F8/30 , G03F7/0045 , Y10S430/111
摘要： A photoresist film superior in etch resistance and PED stability, as well as transmittance to deep UV, having a backbone of polymethylmethacrylate grafted with piperidine moiety of which the nitrogen atom acts as a base.
摘要翻译：具有优异的抗蚀刻性和PED稳定性以及对深紫外线的透光率的光致抗蚀剂膜，其具有以哌啶部分接枝的聚甲基丙烯酸甲酯的骨架，其中氮原子用作碱。

54. 发明授权

US5928820A Method for measuring pattern line width during manufacture of a semiconductor device 失效
标题翻译：在制造半导体器件期间测量图案线宽度的方法
公开(公告)号：US5928820A
公开(公告)日：1999-07-27
申请号：US566373
申请日：1995-12-01
申请人： Ki Yeop Park , Cheol Kyu Bok
发明人： Ki Yeop Park , Cheol Kyu Bok
IPC分类号： G03F7/20 , G03F9/00
CPC分类号： G03F7/70625 , G03F7/70633
摘要： A method for measuring the line width dimensions of a photosensitive film pattern formed during manufacture of a semiconductor device is disclosed. The method uses a photomask which comprises a first auxiliary pattern part having a plurality of first auxiliary patterns separated by a first separation distance therebetween and having substantially the same width dimension as a semiconductor device line pattern formed on a wafer. A second auxiliary pattern part, spaced apart from the first auxiliary pattern part, includes a plurality of second auxiliary patterns separated by a second separation distance therebetween and having substantially the same width dimension as the first auxiliary patterns, the second separation distance being different from the first separation distance. One side of at least one of the second auxiliary patterns is preferably aligned with one side of at least one of the first auxiliary patterns. A larger or smaller width of lines in patterns of the photosensitive film corresponding to these auxiliary patterns of the photomask as observed with a microscope connotes line width dimension information.
摘要翻译：公开了一种用于测量半导体器件制造期间形成的感光膜图案的线宽尺寸的方法。该方法使用光掩模，该光掩模包括第一辅助图案部分，该第一辅助图案部分具有多个第一辅助图案，该第一辅助图案在其间具有第一间隔距离并且具有与形成在晶片上的半导体器件线图案基本相同的宽度尺寸。与第一辅助图案部分间隔开的第二辅助图案部分包括多个第二辅助图案，该第二辅助图案与第一辅助图案部分间隔开第二间隔距离，并具有与第一辅助图案基本上相同的宽度尺寸，第二间隔距离不同于第一分隔距离。第二辅助图案中的至少一个的一侧优选地与至少一个第一辅助图案的一侧对准。与显微镜观察到的对应于光掩模的这些辅助图案的感光膜的图案中的较大或较小宽度的线表示线宽度尺寸信息。

55. 发明授权

US5888698A Photoresist film for deep ultra violet and method for forming photoresist film pattern using the same 失效
公开(公告)号：US5888698A
公开(公告)日：1999-03-30
申请号：US864113
申请日：1997-05-28
申请人： Cha Won Koh , Cheol Kyu Bok
发明人： Cha Won Koh , Cheol Kyu Bok
IPC分类号： G03F7/004 , C08F8/30 , C08F220/02 , C08F220/58 , C08L33/24 , G03F7/039 , G03F7/26 , H01L21/027 , G03C1/73 , B05D3/06
CPC分类号： G03F7/039 , C08F220/58 , C08F8/30 , G03F7/0045 , Y10S430/111
摘要： A photoresist film superior in etch resistance and PED stability, as well as transmittance to deep UV, having a backbone of polymethylmethacrylate grafted with piperidine moiety of which the nitrogen atom acts as a base.

56. 发明申请

US20110256723A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：US20110256723A1
公开(公告)日：2011-10-20
申请号：US12981414
申请日：2010-12-29
申请人： Ki Lyoung LEE , Cheol Kyu Bok , Jung Hyung Lee
发明人： Ki Lyoung LEE , Cheol Kyu Bok , Jung Hyung Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11529
摘要： A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first sacrificial hard mask layer over a semiconductor substrate including an etch layer, forming a first spacer over the first sacrificial hard mask layer, forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer using the first spacer as an etch mask, forming a second spacer at both sidewalls of the first sacrificial hard mask pattern, partially isolating the second spacer, and forming a pad pattern over the second spacer. As a result, a line-and-space pattern such as a control gate of the NAND flash memory and a pad portion coupled to a drain contact in an X-decoder of a peripheral circuit region can be easily implemented.
摘要翻译：公开了一种用于形成半导体器件的方法。一种形成半导体器件的方法包括在包括蚀刻层的半导体衬底上形成第一牺牲硬掩模层，在第一牺牲硬掩模层上形成第一间隔物，通过蚀刻第一牺牲硬掩模形成第一牺牲硬掩模图案层，使用第一间隔物作为蚀刻掩模，在第一牺牲硬掩模图案的两个侧壁处形成第二间隔物，部分地隔离第二间隔物，以及在第二间隔物上形成焊盘图案。结果，可以容易地实现诸如NAND快闪存储器的控制栅极和耦合到外围电路区域的X解码器中的漏极触点的焊盘部分的线间距图案。

57. 发明申请

US20090170336A1 METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件图案的方法
公开(公告)号：US20090170336A1
公开(公告)日：2009-07-02
申请号：US12163817
申请日：2008-06-27
申请人： Keun Do Ban , Cheol Kyu Bok
发明人： Keun Do Ban , Cheol Kyu Bok
IPC分类号： H01L21/308
CPC分类号： H01L21/31144 , H01L21/0334
摘要： A method for forming a pattern of a semiconductor device comprises forming a spacer with an oxide film in a SPT process, and removing the spacer formed to have a horn shape before etching an underlying layer, so that the horn shape is transcribed in a lower portion, thereby facilitating control of critical dimension in etching the underlying layer so as to improve a characteristic of the device.A method for forming a pattern of a semiconductor device of the present invention comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial pattern to remain the spacer; etching the hard mask layer with the spacer as a mask to form a hard mask pattern; removing the spacer; and etching the underlying layer with the hard mask pattern as a mask.
摘要翻译：用于形成半导体器件的图案的方法包括在SPT工艺中形成具有氧化膜的间隔物，并且在蚀刻下面的层之前去除形成为具有喇叭形状的间隔物，使得喇叭形状被转录在下部从而有助于控制蚀刻底层的临界尺寸，以改善器件的特性。一种形成本发明的半导体器件的图案的方法包括：在半导体衬底上形成下层和硬掩模层; 在硬掩模层上形成牺牲图案; 在牺牲图案的两侧形成间隔物; 去除牺牲图案以保持间隔物; 用间隔物作为掩模蚀刻硬掩模层以形成硬掩模图案; 去除间隔物; 并用硬掩模图案作为掩模蚀刻下层。

58. 发明授权

US07550362B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07550362B2
公开(公告)日：2009-06-23
申请号：US11482135
申请日：2006-07-05
申请人： Keun Do Ban , Cheol Kyu Bok
发明人： Keun Do Ban , Cheol Kyu Bok
IPC分类号： H01L21/76
CPC分类号： H01L28/91 , H01L27/10852 , H01L27/10894
摘要： A method for manufacturing a semiconductor device includes forming a sacrificial layer for forming a lower electrode as an amorphous carbon layer in order to prevent collapsing of a cylindrical lower electrode. When an alignment process is not normally performed to arrange photoresist mask pattern for storage electrode and lower electrode contact plug due to optical absorbance of the amorphous carbon layer, a polysilicon layer is further formed over a SiON film used as a hard mask of the amorphous carbon layer, thereby reducing risk of misalignment and performing a stable process for forming a capacitor to increase yield of semiconductor devices.
摘要翻译：一种制造半导体器件的方法包括形成用于形成下电极的牺牲层作为无定形碳层，以防止圆柱形下电极的折叠。当由于无定形碳层的光吸收而不能正常地进行取向处理来设置用于存储电极和下电极接触塞的光致抗蚀剂掩模图案时，在用作无定形碳的硬掩模的SiON膜上进一步形成多晶硅层从而降低未对准的风险，并且执行用于形成电容器的稳定工艺以提高半导体器件的产量。

59. 发明申请

US20080305642A1 METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20080305642A1
公开(公告)日：2008-12-11
申请号：US11948224
申请日：2007-11-30
申请人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
发明人： Ki Lyoung Lee , Cheol Kyu Bok , Keun Do Ban
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/02115 , H01L21/02134 , H01L21/02137 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/0332 , H01L21/0338 , H01L21/3143 , H01L21/3146 , H01L21/31608 , H01L21/3185 , H01L21/32139
摘要： A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.
摘要翻译：一种用于形成半导体器件的精细图案的方法包括在具有下层的半导体衬底上形成包括第一，第二和第三掩模图案的沉积图案，用第三掩模图案侧蚀刻第二掩模图案作为蚀刻阻挡层掩模，去除第三掩模图案，形成曝光第二掩模图案的上部的自旋碳层，执行蚀刻工艺以使作为蚀刻阻挡掩模的自旋 - 碳层曝光下层，并去除碳 - 碳层。

60. 发明申请

US20070264593A1 Method for manufacturing semiconductor device using immersion lithography process 失效
标题翻译：使用浸渍光刻工艺制造半导体器件的方法
公开(公告)号：US20070264593A1
公开(公告)日：2007-11-15
申请号：US11647323
申请日：2006-12-29
申请人： Cheol Kyu Bok , Hyun Sook Jun , Tae Seung Eom
发明人： Cheol Kyu Bok , Hyun Sook Jun , Tae Seung Eom
IPC分类号： G03F7/20
CPC分类号： G03F7/70341
摘要： A method for manufacturing a semiconductor device using an immersion lithography process is disclosed. The immersion lithography process includes forming a photoresist film over an underlying layer of a semiconductor substrate; exposing the photoresist film to light without using an exposure mask; and performing an exposure process using an exposure mask. After exposure using the immersion lithography, a water mark generated from the exposure layer consumes a part of the acid of the exposure layer but the residual acid remains in the exposure layer to prevent generation of pattern defects such as T-top or pattern bridges.
摘要翻译：公开了一种使用浸没式光刻工艺制造半导体器件的方法。浸没式光刻工艺包括在半导体衬底的下层上形成光刻胶膜; 在不使用曝光掩模的情况下将光致抗蚀剂膜曝光; 并使用曝光掩模进行曝光处理。在使用浸渍光刻曝光之后，从曝光层产生的水印消耗曝光层的酸的一部分，但残留的酸残留在曝光层中，以防止图案缺陷如T顶或图案桥的产生。

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