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51. 发明授权

US07393747B2 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07393747B2
公开(公告)日：2008-07-01
申请号：US11337001
申请日：2006-01-23
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

52. 发明授权

US07361951B2 Flash memory having memory section and peripheral circuit section 失效
标题翻译：具有存储器部分和外围电路部分的闪存
公开(公告)号：US07361951B2
公开(公告)日：2008-04-22
申请号：US11259142
申请日：2005-10-27
申请人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
发明人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译：半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

53. 发明授权

US07335938B2 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07335938B2
公开(公告)日：2008-02-26
申请号：US10971161
申请日：2004-10-25
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

54. 发明申请

US20080017911A1 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080017911A1
公开(公告)日：2008-01-24
申请号：US11798888
申请日：2007-05-17
申请人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

55. 发明申请

US20060131638A1 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20060131638A1
公开(公告)日：2006-06-22
申请号：US11337001
申请日：2006-01-23
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

56. 发明申请

US20050199938A1 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050199938A1
公开(公告)日：2005-09-15
申请号：US10971161
申请日：2004-10-25
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

57. 发明授权

US06798038B2 Manufacturing method of semiconductor device with filling insulating film into trench 失效
标题翻译：具有填充绝缘膜的沟槽的半导体器件的制造方法
公开(公告)号：US06798038B2
公开(公告)日：2004-09-28
申请号：US10140941
申请日：2002-05-09
申请人： Atsuhiro Sato , Masayuki Ichige , Seiichi Mori , Yuji Takeuchi , Hiroaki Hazama , Yukio Nishiyama , Hirotaka Ogihara , Naruhiko Kaji
发明人： Atsuhiro Sato , Masayuki Ichige , Seiichi Mori , Yuji Takeuchi , Hiroaki Hazama , Yukio Nishiyama , Hirotaka Ogihara , Naruhiko Kaji
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
摘要翻译：根据HDP技术，在形成在半导体衬底的表面上或上方的沟槽的内表面上开始形成第一氧化硅膜。然后，第一氧化硅膜的沉积在沟槽的开口闭合之前停止。此外，蚀刻沉积在开口附近的第一氧化硅膜，并且根据HDP技术在沉积在沟槽底部的第一氧化硅膜上形成第二氧化硅膜。以这种方式，第一和第二氧化硅膜可以层压在沟槽的底部。

58. 发明授权

US07649221B2 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07649221B2
公开(公告)日：2010-01-19
申请号：US11951026
申请日：2007-12-05
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

59. 发明授权

US07494869B2 Semiconductor integrated circuit device and manufacturing method thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07494869B2
公开(公告)日：2009-02-24
申请号：US11338707
申请日：2006-01-25
申请人： Atsuhiro Sato
发明人： Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , G11C11/5621 , G11C16/0483 , H01L21/76232 , H01L27/11521 , H01L27/11524
摘要： A manufacturing method of a semiconductor integrated circuit device is disclosed. A gate insulating film is formed on a semiconductor substrate. A first film used as floating gates is formed on the gate insulating film. Trenches are formed in the substrate through the first film. Insulating materials are embedded in the trenches. The insulating materials are set back at least in a plane direction. Second films used as floating gates are formed between the side walls of the insulating materials without making directly contact with the side walls of the insulating materials. The insulating materials are set back from spaces caused between the insulating materials and the second films.
摘要翻译：公开了一种半导体集成电路器件的制造方法。在半导体衬底上形成栅极绝缘膜。在栅极绝缘膜上形成用作浮栅的第一膜。通过第一膜在基板中形成沟槽。绝缘材料嵌入沟槽中。绝缘材料至少在平面方向回缩。在绝缘材料的侧壁之间形成用作浮栅的第二膜，而不与绝缘材料的侧壁直接接触。绝缘材料从绝缘材料和第二薄膜之间的空间回放。

60. 发明申请

US20060258092A1 Semiconductor integrated circuit device and manufacturing method thereof 失效
公开(公告)号：US20060258092A1
公开(公告)日：2006-11-16
申请号：US11338707
申请日：2006-01-25
申请人： Atsuhiro Sato
发明人： Atsuhiro Sato
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28273 , G11C11/5621 , G11C16/0483 , H01L21/76232 , H01L27/11521 , H01L27/11524
摘要： A manufacturing method of a semiconductor integrated circuit device is disclosed. A gate insulating film is formed on a semiconductor substrate. A first film used as floating gates is formed on the gate insulating film. Trenches are formed in the substrate through the first film. Insulating materials are embedded in the trenches. The insulating materials are set back at least in a plane direction. Second films used as floating gates are formed between the side walls of the insulating materials without making directly contact with the side walls of the insulating materials. The insulating materials are set back from spaces caused between the insulating materials and the second films.

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