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51. 外观设计

USD478617S1 Toner cartridge 失效
公开(公告)号：USD478617S1
公开(公告)日：2003-08-19
申请号：US29171295
申请日：2002-11-20
申请人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki
设计人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki

52. 外观设计

USD478344S1 Toner cartridge 失效
公开(公告)号：USD478344S1
公开(公告)日：2003-08-12
申请号：US29171296
申请日：2002-11-20
申请人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki
设计人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki

53. 发明授权

US06555882B2 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US06555882B2
公开(公告)日：2003-04-29
申请号：US09943444
申请日：2001-08-31
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

54. 发明授权

US06535435B2 Reference voltage generator permitting stable operation 有权
标题翻译：参考电压发生器允许稳定运行
公开(公告)号：US06535435B2
公开(公告)日：2003-03-18
申请号：US10012522
申请日：2001-12-12
申请人： Hitoshi Tanaka , Masakazu Aoki , Shinichiro Kimura , Hiromasa Noda , Tomonori Sekiguchi
发明人： Hitoshi Tanaka , Masakazu Aoki , Shinichiro Kimura , Hiromasa Noda , Tomonori Sekiguchi
IPC分类号： G11C700
CPC分类号： H01L27/0222 , G11C5/145 , G11C5/147 , G11C11/4074 , H01L27/10897
摘要： A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.
摘要翻译：提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。它还允许在电源打开时快速启动并提供高稳定性。

55. 发明授权

US06473354B2 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06473354B2
公开(公告)日：2002-10-29
申请号：US10040492
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

56. 发明授权

US06424586B1 Semiconductor integrated circuit device and method of activating same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US06424586B1
公开(公告)日：2002-07-23
申请号：US10040435
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线之间的并行形式提供多个开关MOSFET，其不需要在其非正常状态下的存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

57. 发明授权

US06257855B1 Screw fluid machine 有权
标题翻译：螺旋流体机
公开(公告)号：US06257855B1
公开(公告)日：2001-07-10
申请号：US09442467
申请日：1999-11-18
申请人： Hirotaka Kameya , Shigekazu Nozawa , Masayuki Urashin , Takeshi Hida , Masakazu Aoki
发明人： Hirotaka Kameya , Shigekazu Nozawa , Masayuki Urashin , Takeshi Hida , Masakazu Aoki
IPC分类号： F03C200
CPC分类号： F04C18/084 , F04C18/16
摘要： A screw rotor for use in screw compressors and screw vacuum pumps comprises a pair of rotors including a male rotor and a female rotor. These rotors have helical lobes in an axial direction and mesh with each other to form a compression chamber. Depending upon a lobe configuration of the rotors, suction pressure and discharge pressure, a negative torque for self-rotation as well as a positive torque opposing to rotation due to a compression action is generated on the female rotor in operation. This phenomenon generates when a value obtained by integrating a torque acting on the female rotor over an entire cross section in an axial direction of the rotors becomes negative. When the negative torque is generated, noises due to tooth separating vibration is caused. Then, a lobe profile is defined such that a magnitude of the negative torque is smaller than that of the positive torque in respective cross sections of the female rotor. That is, a relationship between a radius of a point of contact on a leading surface side of the female rotor and a radius of a point of contact on a trailing surface side or curvatures of the rotors are such that the negative torque is not generated on the lobe profile.
摘要翻译：用于螺杆式压缩机和螺杆式真空泵的螺杆转子包括一对转子，包括一个公转子和一个母转子。这些转子在轴向上具有螺旋形叶片并且彼此啮合以形成压缩室。根据转子的凸角构造，吸入压力和排出压力，在操作中在母转子上产生自旋转的负转矩以及由于压缩动作而与旋转相反的正转矩。当通过将在母转子上作用的转矩在转子的轴向上的整个横截面上积分得到的值变为负时，会产生这种现象。当产生负转矩时，会引起由于齿分离振动引起的噪音。然后，定义凸角轮廓，使得负转矩的大小小于阴转子的相应横截面中的正转矩的大小。也就是说，阴转子的前表面侧的接触点的半径与后表面侧的接触点的半径或转子的曲率之间的关系使得不产生负转矩肺叶剖面。

58. 发明授权

US6104056A Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US6104056A
公开(公告)日：2000-08-15
申请号：US126437
申请日：1998-07-30
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L21/8247 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/04 , G11C16/28 , H01L21/28 , H01L21/336 , H01L27/01 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/036 , H01L31/062 , H01L31/112 , H01L31/113 , H01L21/119
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/7888 , G11C2216/06 , G11C2216/08 , H01L27/1203 , H01L29/785
摘要： A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.
摘要翻译：一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。根据一个实施例，提供了从沟道分离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。

59. 发明授权

US5966336A Semiconductor device having redundancy circuit 有权
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US5966336A
公开(公告)日：1999-10-12
申请号：US144258
申请日：1998-08-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access memory (DRAM) having a memory array which is divided into memory mats and a storage capacity of 16 mega bits or more. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：为半导体存储器引入冗余技术，更具体地说，涉及一种用于存储器的冗余技术，例如具有存储器阵列的动态随机存取存储器（DRAM），该存储器阵列被分成存储器阵列，存储容量为16兆比特或者更多。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与存储的缺陷地址进行比较的存储器。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

60. 发明授权

US5880604A Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US5880604A
公开(公告)日：1999-03-09
申请号：US714994
申请日：1996-09-17
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H01L27/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/094 , H03K19/20 , H03K19/0948 , H03K19/096
CPC分类号： H03K3/356113 , H03K19/0016 , H01L27/0218
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

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