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51. 发明授权

US08811080B2 Flash memory system and word line interleaving method thereof 有权
标题翻译：闪存系统及其字线交错方法
公开(公告)号：US08811080B2
公开(公告)日：2014-08-19
申请号：US13236176
申请日：2011-09-19
申请人： Yongjune Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong
发明人： Yongjune Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong
IPC分类号： G11C11/06
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/1157 , H01L27/11582
摘要： Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
摘要翻译：提供一种闪速存储器系统及其字线交错方法。闪存系统包括存储单元阵列和字线交错逻辑。存储单元阵列连接到多个字线。字线（WL）交织逻辑对与至少两个不同字线对应的WL数据和包括交错数据的编程数据执行对存储单元阵列的交织操作。

52. 发明授权

US08711624B2 Memory device and self interleaving method thereof 有权
标题翻译：存储器件及其自交插方法
公开(公告)号：US08711624B2
公开(公告)日：2014-04-29
申请号：US13236249
申请日：2011-09-19
申请人： Seonghyeog Choi , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
发明人： Seonghyeog Choi , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/3404
摘要： A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
摘要翻译：存储器装置包括存储单元阵列，配置成使用交织方案将数据进行交错和加载到缓冲电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。

53. 发明授权

US08700974B2 Memory system controller having seed controller using multiple parameters 有权
标题翻译：存储器系统控制器，具有使用多个参数的种子控制器
公开(公告)号：US08700974B2
公开(公告)日：2014-04-15
申请号：US13616168
申请日：2012-09-14
申请人： Jungsoo Chung , Hong Rak Son , Junjin Kong
发明人： Jungsoo Chung , Hong Rak Son , Junjin Kong
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F12/0238 , G06F2212/1032 , G06F2212/7202 , G06F2212/7208 , G11C7/1006
摘要： In a memory system, a memory controller includes a randomizer and a seed controller. The seed controller provides a seed to the randomizer and includes; a first register block performing a first cyclic shift operation using a first parameter related to the nonvolatile memory device, a second register block performing a second cyclic shift operation using a second parameter related to the nonvolatile memory device, and a seed generating block generating the seed from the first and second cyclic shift results.
摘要翻译：在存储器系统中，存储器控制器包括随机化器和种子控制器。种子控制器为随机发生器提供种子，包括; 使用与非易失性存储器件相关的第一参数执行第一循环移位操作的第一寄存器块，使用与非易失性存储器件相关的第二参数执行第二循环移位操作的第二寄存器块，以及生成种子的种子生成块从第一和第二循环移位结果。

54. 发明授权

US08635512B2 Memory system with page-based iterative decoding structure and page-based iterative decoding method thereof 有权
标题翻译：具有基于页面的迭代解码结构和基于页面的迭代解码方法的存储器系统
公开(公告)号：US08635512B2
公开(公告)日：2014-01-21
申请号：US13110395
申请日：2011-05-18
申请人： Kijun Lee , Hong Rak Son , Junjin Kong
发明人： Kijun Lee , Hong Rak Son , Junjin Kong
IPC分类号： H03M13/00 , G06F11/00 , G08C25/00 , G11B27/00
CPC分类号： H03M13/2951 , G06F11/1008 , H03M13/2948
摘要： A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful completion of iterative decoding corresponding to a current sector of the N sectors, immediately initiating iterative decoding a next sector of the N sectors.
摘要翻译：提供了一种迭代地解码通过信道传送的数据的方法。该方法可以包括以连续顺序迭代地解码数据的1至N个扇区的每个扇区，直到所有N个扇区被解码，其中在确定对应于N个扇区的当前扇区的迭代解码的成功完成时，立即启动迭代解码 N部门的下一个部门。

55. 发明申请

US20120069657A1 MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF 有权
标题翻译：存储器件及其自动交错方法
公开(公告)号：US20120069657A1
公开(公告)日：2012-03-22
申请号：US13236249
申请日：2011-09-19
申请人： Seonghyeog CHOI , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
发明人： Seonghyeog CHOI , Hong Rak Son , Junjin Kong , Jaehong Kim , KyoungLae Cho , Yong June Kim
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/3404
摘要： A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
摘要翻译：存储器装置包括存储单元阵列，配置成使用交织方案将数据交错和加载到缓冲器电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。

56. 发明申请

US20110283166A1 STORAGE DEVICE HAVING A NON-VOLATILE MEMORY DEVICE AND COPY-BACK METHOD THEREOF 有权
标题翻译：具有非易失性存储器件的存储器件及其复制方法
公开(公告)号：US20110283166A1
公开(公告)日：2011-11-17
申请号：US13106892
申请日：2011-05-13
申请人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
发明人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/106 , H03M13/1102 , H03M13/136 , H03M13/152 , H03M13/155 , H03M13/2909 , H03M13/618
摘要： A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.
摘要翻译：存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控制器非易失性存储器件。存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

57. 发明申请

US20110216588A1 MULTI-BIT CELL MEMORY DEVICES USING ERROR CORRECTION CODING AND METHODS OF OPERATING THE SAME 有权
标题翻译：使用错误校正编码的多位单元存储器件及其操作方法
公开(公告)号：US20110216588A1
公开(公告)日：2011-09-08
申请号：US13039004
申请日：2011-03-02
申请人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
发明人： Yong June Kim , Jaehong Kim , Junjin Kong , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04
摘要： A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.
摘要翻译：存储器件包括多个多位存储器单元。根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。码字的比特组可以是连续比特的组。在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

58. 发明申请

US20100202198A1 Semiconductor memory device and data processing method thereof 有权
标题翻译：半导体存储器件及其数据处理方法
公开(公告)号：US20100202198A1
公开(公告)日：2010-08-12
申请号：US12654578
申请日：2009-12-23
申请人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
发明人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
IPC分类号： G11C16/04
CPC分类号： G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.
摘要翻译：提供了一种半导体存储器件中的数据处理方法。数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

59. 发明授权

US09905299B2 Nonvolatile memory device and operating method of nonvolatile memory device 有权
公开(公告)号：US09905299B2
公开(公告)日：2018-02-27
申请号：US15370079
申请日：2016-12-06
申请人： Changkyu Seol , Junjin Kong , Youngsuk Ra , Hyejeong So , Hong Rak Son
发明人： Changkyu Seol , Junjin Kong , Youngsuk Ra , Hyejeong So , Hong Rak Son
IPC分类号： G11C16/04 , G11C16/14 , G11C16/08 , G11C16/26
CPC分类号： G11C16/14 , G11C11/5628 , G11C11/5635 , G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648
摘要： A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a row decoder circuit connected to the memory cell array through a plurality of word lines; and a page buffer circuit connected to the memory cell array through bit lines. The row decoder circuit applies read voltages to a selected word line during a read operation. During a read operation performed with respect to each of N logical pages (N being a positive integer) of memory cells connected to the selected word line, the row decoder circuit applies a read voltage from among adjacent N read voltages to the selected word line without applying read voltages other than the adjacent N read voltages to the selected word line. The adjacent N read voltages include a second highest read voltage among the read voltages.

60. 发明授权

US09218159B2 Memory system generating random number and method generating random number 有权
标题翻译：存储系统产生随机数和产生随机数的方法
公开(公告)号：US09218159B2
公开(公告)日：2015-12-22
申请号：US13685743
申请日：2012-11-27
申请人： Changkyu Seol , Junjin Kong , Hong Rak Son , Pilsang Yoon
发明人： Changkyu Seol , Junjin Kong , Hong Rak Son , Pilsang Yoon
IPC分类号： H04L9/08 , G06F7/58
CPC分类号： G06F7/58 , G06F7/588 , H04L9/08 , H04L9/0869 , H04L2209/12
摘要： In a memory of non-volatile memory cells, a random number is generated by programming non-volatile memory cells, reading the programmed non-volatile memory cells using a random number read voltage selected in accordance with a characteristic of the non-volatile memory cells to generate random read data, and generating the random number from the random read data.
摘要翻译：在非易失性存储器单元的存储器中，通过编程非易失性存储器单元来产生随机数，使用根据非易失性存储器单元的特性选择的随机数读取电压读取编程的非易失性存储器单元生成随机读取数据，并从随机读取数据生成随机数。

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