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51. 发明授权

US06693980B1 Wideband fast-hopping receiver front-end and mixing method 有权
标题翻译：宽带快跳接收机前端和混合方式
公开(公告)号：US06693980B1
公开(公告)日：2004-02-17
申请号：US09664298
申请日：2000-09-18
申请人： Lloyd F. Linder , Don C. Devendorf
发明人： Lloyd F. Linder , Don C. Devendorf
IPC分类号： H04L2722
CPC分类号： H03D7/165
摘要： A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.
摘要翻译：宽带快速跳频接收机前端使用直接数字合成（DDS）向前端的混频器提供正交LO信号。 DDS电路存储表示所需波形的多个数字字序列，并响应于时钟信号和命令信号将期望的序列对输出到一对DAC。 DAC将序列转换为模拟信号，根据需要进行滤波和平方以向混频器提供正交LO信号。通过改变命令信号来实现跳频，这导致输出不同的序列对，并且提供给混频器的LO信号的频率被改变。主动图像抑制与DDS LO生成相结合，提供更快的跳频。前端与ADC和通信信号处理器相结合，提供一个完整的系统，所有系统都可以集成在一个共同的基板上。

52. 发明授权

US5859558A Low voltage analog front end 失效
标题翻译：低压模拟前端
公开(公告)号：US5859558A
公开(公告)日：1999-01-12
申请号：US827855
申请日：1997-04-11
申请人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf
发明人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf
IPC分类号： H03D7/14 , H03F3/343 , H03F3/45 , G06G7/12
CPC分类号： H03F3/45071 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F3/343 , H03D2200/0033 , H03D2200/0043
摘要： A low voltage analog front end (AFE) includes a differential transistor pair which converts an input voltage, typically A.C.-coupled to the pair's control inputs, to a differential current. Impedance networks connected to each transistor's control input are joined together at a common node, and a current source is connected to the node which causes DC bias currents to be mirrored through the pair's current circuits, so that the AFE's differential output current comprises a differential current produced by the pair in response to an input voltage and superimposed on the DC bias currents. The current source preferably generates mirrored currents which are larger than its reference current to linearize the pair's response and to provide the AFE with a wide dynamic range. An input to the AFE sees a low impedance which is about equal to the sum of the impedance networks, which can be resistive or complex as needed. The AFE has widespread application as a front end circuit, serving as a low voltage input stage for a Gilbert mixer, for example. By generating bias currents via the pair's control inputs, supply voltage headroom requirements are reduced, improving a system's dynamic range and/or enabling the use of lower voltage power supplies. The AFE can be configured as either a differential or single-ended voltage-to-differential current converter.
摘要翻译：低电压模拟前端（AFE）包括差分晶体管对，其将输入电压（通常与耦合到对的控制输入的交流耦合）转换为差分电流。连接到每个晶体管的控制输入的阻抗网络在公共节点处连接在一起，并且电流源连接到节点，其导致DC偏置电流通过该对电流电路被镜像，使得AFE的差分输出电流包括差分电流由输出电压响应输入电压产生并叠加在直流偏置电流上。电流源优选地产生大于其参考电流的镜像电流，以使对的响应线性化并为AFE提供宽的动态范围。 AFE的输入端看到一个低阻抗，大约等于阻抗网络的总和，根据需要可以阻抗或复杂。 AFE作为前端电路广泛应用，例如用作Gilbert混频器的低电压输入级。通过经由该对的控制输入产生偏置电流，降低了电源电压余量要求，提高系统的动态范围和/或使能低电压电源。 AFE可以配置为差分或单端电压 - 差分电流转换器。

53. 发明授权

US09813030B1 Wideband single-ended IM3 distortion nulling 有权
公开(公告)号：US09813030B1
公开(公告)日：2017-11-07
申请号：US15201206
申请日：2016-07-01
申请人： Wais M. Ali , Lloyd F. Linder
发明人： Wais M. Ali , Lloyd F. Linder
IPC分类号： H03F1/22 , H03F1/32 , H03F3/195 , H03F1/26
CPC分类号： H03F1/3205 , H03F1/223 , H03F1/26 , H03F1/3223 , H03F3/195 , H03F2200/411 , H03F2200/451 , H03F2201/3212
摘要： System-on-chip (SOC) products using high frequency, wideband, highly linear, CMOS and BiCMOS processes will be the next evolution of wireless and wireline communications integrated circuits. Aspects described herein can provide enhanced overall performance over existing prior art single-ended, wideband RF amplifier topologies. A single-ended third order intermodulation distortion nulling circuit can extend the dynamic range for wideband amplifiers up to an order-of-magnitude, without a DC power or noise figure (NF) penalty. The application of distortion nulling can be extended to all the building blocks used in CMOS/BiCMOS RF transceivers to improve performance. The application of this concept to all of the building blocks in an RF transceiver will allow the dynamic range of the transceiver to be increased without suffering a DC power dissipation increase or a significant noise increase.

54. 发明授权

US06931083B1 Low noise, low distortion, muxable Gilbert mixer signal processing system and method with AGC functionality 有权
标题翻译：低噪声，低失真，可混合的吉尔伯特混频器信号处理系统和具有AGC功能的方法
公开(公告)号：US06931083B1
公开(公告)日：2005-08-16
申请号：US09579596
申请日：2000-05-26
申请人： Lloyd F. Linder , Clifford N. Duong , Don C. Devendorf
发明人： Lloyd F. Linder , Clifford N. Duong , Don C. Devendorf
IPC分类号： H03D7/00 , H03D7/14 , H04B1/16 , H04B1/26 , H04L27/08
CPC分类号： H03D7/1433 , H03D7/1425 , H03D7/1458 , H03D7/1491
摘要： A signal processing system and method. The inventive system includes a first circuit for distributing an input signal between two or more channels in a current mode of operation. A second circuit is disposed in each of the channels for processing the input signal and providing an output signal in response thereto. A third circuit is provided to combine the signals output by the processing circuit. A fourth circuit is included for controlling the first and the third circuits. In a specific illustrative embodiment, the system further includes a radio frequency stage for downconverting a received signal and providing the input signal in response thereto. In the specific embodiment, the first circuit includes a mixing circuit. The mixing circuit includes Gilbert cells and circuitry for providing automatic gain control for each of the channels individually. The Gilbert cells and the automatic gain control circuitry are driven by a transconductance amplifier and therefore operate in a current mode. Differential digital automatic gain control signals are provided in response to a channel select signal from a digital control circuit. The inventive circuit provides multiple IF channels which may be filtered individually. The invention thereby provides wide band operation in a simple, single stage implementation that consumes little power. Further, the current mode thereof is effective in the reduction of insertion loss.
摘要翻译：信号处理系统及方法。本发明的系统包括用于在当前操作模式中在两个或更多个通道之间分配输入信号的第一电路。在每个通道中设置第二电路以处理输入信号并响应于此提供输出信号。提供第三电路以组合由处理电路输出的信号。包括用于控制第一和第三电路的第四电路。在具体的说明性实施例中，该系统还包括用于下变频接收信号并响应于此提供输入信号的射频级。在具体实施例中，第一电路包括混合电路。混合电路包括吉尔伯特单元和用于单独为每个通道提供自动增益控制的电路。吉尔伯特单元和自动增益控制电路由跨导放大器驱动，因此在当前模式下工作。响应于来自数字控制电路的通道选择信号提供差分数字自动增益控制信号。本发明的电路提供可以单独过滤的多个IF信道。因此，本发明在消耗很少功率的简单的单级实现中提供宽带操作。此外，其电流模式在减少插入损耗方面是有效的。

55. 发明授权

US06636730B2 Wideband IF image rejecting receiver 失效
标题翻译：宽带IF图像拒绝接收机
公开(公告)号：US06636730B2
公开(公告)日：2003-10-21
申请号：US09220288
申请日：1998-12-23
申请人： Thomas A. Spargo , Lloyd F. Linder , Matthew S. Gorder
发明人： Thomas A. Spargo , Lloyd F. Linder , Matthew S. Gorder
IPC分类号： H04B112
CPC分类号： H03D3/007
摘要： A system and method for effecting wideband image rejection. In a receiver implementation, the inventive method includes the steps of receiving a first signal in a first frequency band and generating in-phase and quadrature signals therefrom. The phase of the in-phase signal is shifted to provide a second signal and the phase of the quadrature signal is shifted to provide a third signal. A predetermined phase relationship is thereby effected between the second and the third signals. The second and third signals are then summed to provide an output signal which has minimal interference from a mixing signal. In an illustrative receiver application, the phase shifting is achieved via the use of all pass networks. Each of the all pass networks include a differential amplifier having first and second input terminals. The first and the second terminals are connected to a first end of first and second resistive elements, respectively. The second ends of the first and second resistive elements are connected to a common input terminal for the network. The first input terminal is a negative terminal and is connected to an output terminal of the network. The second terminal is a positive terminal and is connected to a source of ground potential via a capacitive element.
摘要翻译：一种用于实现宽带镜像抑制的系统和方法。在接收机实现中，本发明的方法包括以下步骤：在第一频带中接收第一信号，并从中产生同相和正交信号。同相信号的相位被移位以提供第二信号，并且正交信号的相位被移位以提供第三信号。从而在第二和第三信号之间实现预定的相位关系。然后将第二和第三信号相加以提供具有来自混合信号的最小干扰的输出信号。在说明性的接收机应用中，通过使用所有通过网络来实现相移。所有通过网络中的每一个包括具有第一和第二输入端的差分放大器。第一和第二端子分别连接到第一和第二电阻元件的第一端。第一和第二电阻元件的第二端连接到用于网络的公共输入端。第一输入端子是负极端子，并连接到网络的输出端子。第二端子是正极端子，并且经由电容元件连接到地电位源。

56. 发明授权

US06580383B1 High resolution ADC based on an oversampled subranging ADC 有权
标题翻译：基于过采样subranging ADC的高分辨率ADC
公开(公告)号：US06580383B1
公开(公告)日：2003-06-17
申请号：US09703646
申请日：2000-11-01
申请人： Don C. Devendorf , Benjamin Felder , Lloyd F. Linder
发明人： Don C. Devendorf , Benjamin Felder , Lloyd F. Linder
IPC分类号： H03M300
CPC分类号： H03M1/20
摘要： A high performance ADC apparatus. The inventive apparatus comprises a front end ADC baseline device providing a baseline bit size at a baseline data rate and a selected dynamic range at a baseline clock rate. A first circuit is enabled for translating upward, by a selected factor, a reference clock to produce the baseline clock rate. A second circuit is enabled for decimating the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. A final circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with the final resolution. The method for producing this result includes providing the baseline device having a selected dynamic range at a baseline clock rate; generating the baseline clock rate by translating a reference clock upward by a selected factor; decimating the data rate of the baseline device to a slower data rate so as to achieve a selected degree of oversampling; and producing an output data rate as a sub-multiple of the baseline clock rate with the selected output resolution at the slower data rate. The architecture includes a monolithic substrate on which the baseline ADC provides a dynamic range necessary to satisfy the performance requirements of the final ADC.
摘要翻译：高性能ADC装置。本发明的装置包括前端ADC基线装置，以基线数据速率提供基线比特大小，并以基线时钟速率提供选定的动态范围。启用第一电路，通过选择的因子向上平移参考时钟以产生基线时钟速率。启用第二电路，用于将基线设备的基线数据速率抽取到所选因子减少的数据速率，以便实现等于所选因子的过采样率。采用最终电路用最终分辨率产生的输出数据速率小于基准时钟速率。用于产生该结果的方法包括：以基线时钟速率提供具有选定动态范围的基线装置; 通过将参考时钟向上转换所选因子来产生基线时钟速率; 将基线设备的数据速率抽取成较慢的数据速率，以便实现选定的过采样度; 并且以较慢的数据速率产生具有所选择的输出分辨率的基线时钟速率的子倍数的输出数据速率。该架构包括单片基板，基准ADC提供满足最终ADC性能要求所需的动态范围。

57. 发明授权

US5315231A Symmetrical bipolar bias current source with high power supply rejection ratio (PSRR) 失效
标题翻译：具有高电源抑制比（PSRR）的对称双极偏置电流源
公开(公告)号：US5315231A
公开(公告)日：1994-05-24
申请号：US976760
申请日：1992-11-16
申请人： Lloyd F. Linder , Dwight D. Birdsall , Kelvin T. Tran
发明人： Lloyd F. Linder , Dwight D. Birdsall , Kelvin T. Tran
IPC分类号： H03F3/45 , H03F1/30 , H03F3/26 , H03F3/30 , G05F3/26
CPC分类号： H03F1/307 , H03F3/26
摘要： A bandgap reference voltage source (104) has positive and negative terminals (104a,104b) which are connected through high impedance constant current sources (124c,126c) to positive and negative voltage supplies (+VDD,-VEE) respectively. The effect of variations of the voltage supplies (+VDD, -VEE) on the voltage source (104) is low due to the high impedances of the currents sources (124c,126c), providing a high power supply rejection ratio (PSRR). The reference voltage (VREF) generated by the voltage source (104) is converted into a reference current (IREF) which flows through two equal series resistors (108,110), and also through current mirrors (124,126) which produce positive and negative output currents corresponding thereto. The current sources (124c,126c) for the voltage source (104) are also controlled by the current mirrors (124,126). A servo control amplifier (232) senses the voltage at the junction (234) of the resistors (108,110) and adjusts the voltage at either the positive or negative terminal (104a,104b) of the voltage source (104) to maintain the voltages at the terminals (104a,104b) symmetrical with respect to ground, thereby preventing the voltage source (104) from latching to one of the voltage supplies (+VDD,-VEE) during startup.
摘要翻译：带隙参考电压源（104）具有分别通过高阻抗恒流源（124c，126c）连接到正和负电压源（+ VDD，-VEE）的正端子和负端子（104a，104b）。由于电流源（124c，126c）的高阻抗提供高电源抑制比（PSRR），电压源（+ VDD，-VEE）的变化对电压源（104）的影响很小。由电压源（104）产生的参考电压（VREF）被转换成流过两个相等的串联电阻（108,110）的参考电流（IREF），并且还通过电流镜（124,126）产生正和负的输出电流对应到此。用于电压源（104）的电流源（124c，126c）也由电流镜（124,126）控制。伺服控制放大器（232）感测电阻器（108,110）的结（234）处的电压，并且调节电压源（104）的正或负端子（104a，104b）处的电压，以将电压维持在端子（104a，104b）相对于地面对称，从而防止电压源（104）在启动期间锁定到电压源（+ VDD，-VEE）之一。

58. 发明授权

US5250911A Single-ended and differential transistor amplifier circuits with full signal modulation compensation techniques which are technology independent 失效
标题翻译：具有完全信号调制补偿技术的单端和差分晶体管放大器电路是技术独立的
公开(公告)号：US5250911A
公开(公告)日：1993-10-05
申请号：US871861
申请日：1992-04-20
申请人： Lloyd F. Linder , Dwight D. Birdsall
发明人： Lloyd F. Linder , Dwight D. Birdsall
IPC分类号： H03F1/32 , H03F3/30 , H03F3/45 , H03F3/50 , H03F1/14
CPC分类号： H03F1/3211 , H03F1/3217 , H03F1/3276 , H03F3/3081 , H03F3/45071 , H03F3/45098 , H03F3/50 , H03F3/505 , H03F2203/45578 , H03F2203/45611 , H03F2203/45612 , H03F2203/45641 , H03F2203/45721
摘要： A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin+V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation .DELTA.Vce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current .DELTA.Iload which is equal and opposite to the load current variation caused by a change (.DELTA.Vin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation .DELTA.Vbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (.DELTA.Ib) which is equal and opposite to a non-linear base current variation to the emitter or collector of the main transistor (Q3) to compensate for current gain modulation .DELTA.Ib. The modulation compensation arrangements are applicable to common-collector, commonbase and common emitter amplifiers in single-ended and differential configurations, and to substantially all bipolar and field-effect transistor technologies.

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