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51. 发明授权

US06317812B1 Device and method for controlling solid-state memory system 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US06317812B1
公开(公告)日：2001-11-13
申请号：US09657369
申请日：2000-09-08
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F1200
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件阵列，其经由具有极少线路的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。序列化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个内存设备都由阵列装载分配一个阵列地址。通过在设备总线上广播的适当地址来选择存储设备，而不需要通常的专用选择信号。保留阵列安装配置用于无条件地选择安装的设备。通过设备总线广播的保留地址将取消所有先前选择的存储设备。通过读取流技术增强读取性能，其中当当前大量数据被序列化并从存储器子系统移出到控制器模块时，控制器模块还设置下一个数据块的地址以开始寻址内存系统。

52. 发明授权

US06148363A Device and method for controlling solid-state memory system 失效
公开(公告)号：US06148363A
公开(公告)日：2000-11-14
申请号：US64528
申请日：1998-04-21
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16 , G06F13/42 , G11C5/00 , G11C5/06 , G11C8/12 , G06F12/00
CPC分类号： G11C5/04 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G11C5/00 , G11C5/066 , G11C8/12 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

53. 发明授权

US5657332A Soft errors handling in EEPROM devices 失效
标题翻译： EEPROM器件中的软错误处理
公开(公告)号：US5657332A
公开(公告)日：1997-08-12
申请号：US406677
申请日：1995-03-20
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G06F11/10 , G11C16/10 , G11C29/50 , G11C29/52 , G11C29/00 , G11C11/34
CPC分类号： G11C29/028 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

54. 发明授权

US5532962A Soft errors handling in EEPROM devices 失效
公开(公告)号：US5532962A
公开(公告)日：1996-07-02
申请号：US408109
申请日：1995-03-21
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G06F11/10 , G11C16/34 , G11C29/50 , G11C29/00
CPC分类号： G06F11/1008 , G11C16/3418 , G11C16/3431 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/028 , G11C29/50 , G11C29/50004 , G06F2201/81 , G11C16/04
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

55. 发明授权

US08745355B2 Method for assigning addresses to memory devices 失效
标题翻译：为地址分配给存储设备的方法
公开(公告)号：US08745355B2
公开(公告)日：2014-06-03
申请号：US12236919
申请日：2008-09-24
申请人： Robert D. Norman , Vinod C. Lakhani
发明人： Robert D. Norman , Vinod C. Lakhani
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F13/1694 , G06F12/0661
摘要： A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
摘要翻译：一种存储器系统，具有存储器控制器和通过系统总线连接到控制器的几个单独的存储器件。存储器件各自包括存储器单元阵列，用于寻址单元的寻址电路和存储每个存储器件唯一的本地地址的地址存储电路。通过选择设备中的第一个并将地址分配命令转发到所选择的设备，将本地地址依次分配给存储器设备。已经检测到地址分配命令的命令解码器将允许由控制器放置在总线上的本地地址被加载到所选择的存储器件中。该序列将继续，直到所有存储器件都被分配了本地地址，此时可以访问存储器件以执行存储器读取，编程，擦除和其他操作。

56. 发明授权

US08369145B2 Apparatus and method for detecting over-programming condition in multistate memory device 失效
标题翻译：多状态存储器件中过度编程条件的检测装置及方法
公开(公告)号：US08369145B2
公开(公告)日：2013-02-05
申请号：US13410771
申请日：2012-03-02
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G11C11/34
CPC分类号： G11C29/765 , G06F11/1072 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/04 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/00 , G11C29/52 , G11C29/76 , G11C29/82 , G11C2029/0409 , G11C2211/5643
摘要： A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.
摘要翻译：系统实施例包括非易失性存储器件，存储器和控制器。非易失性存储器件包括多个非易失性存储单元。每个非易失性存储器单元适于存储至少两个位。存储器适于在系统上电时存储程序。控制器适于实现程序以提供用于编程和擦除非易失性存储器单元的指令。方法实施例包括在为存储器系统加电时将程序加载到存储器中，以及使用包括编程和擦除多位非易失性存储器单元的控制器来实现程序。

57. 发明授权

US07353325B2 Wear leveling techniques for flash EEPROM systems 失效
标题翻译：闪存EEPROM系统的磨损均衡技术
公开(公告)号：US07353325B2
公开(公告)日：2008-04-01
申请号：US11028882
申请日：2005-01-03
申请人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
发明人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
IPC分类号： G06F12/02
CPC分类号： G11C16/3495 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C8/12 , G11C16/349
摘要： A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
摘要翻译：由闪存电可擦除和可编程只读存储器（“EEPROM”）组成的块的大容量存储系统被组合成块，这些块又被分组到存储体中，以便管理存储器经历的擦除和重写周期的数量银行为了延长内存系统的使用寿命。由于这种类型的存储器单元在有限数量的擦除和重写周期之后变得不可用，尽管在数万个周期中，避免了不均匀地使用存储器组，使得整个存储器不会变得不起作用，因为它的一个存储体具有达到了终点，而其他银行也没有被使用。监视存储器组的相对使用，并且响应于不均匀使用的检测，使它们的物理地址彼此周期性交换，以便在存储器的使用寿命期内甚至使用它们。

58. 发明授权

US06749533B2 Gearbox 有权
标题翻译：变速箱
公开(公告)号：US06749533B2
公开(公告)日：2004-06-15
申请号：US10153600
申请日：2002-05-24
申请人： Robert D. Norman
发明人： Robert D. Norman
IPC分类号： F16H5708
CPC分类号： F16H57/08 , B25J9/102 , B25J17/0241 , B64G1/22 , F16H1/46 , F16H2057/0335 , Y10T74/20329
摘要： A joint may have a multi-stage planetary gearbox between the stationary housing and the rotary housing. To accommodate different gear ratios, the rotary housing may be joined to the stationary housing by a releasable attachment. This allows portions of the planetary gearbox to be replaced so that, for instance, the last stage may be chosen as either a simple or compound differential planetary stage. To allow for different capacities, a quotient of a sum of all teeth of a sun gear of a stage and of the ring gear with which the planetary gears of the stage mesh to both the number three and the number four yields an integer. In this way, the stage may be provided with either three or four planetary gears. The gearbox may have a ring gear common to a plurality of simple planetary stages. Where the final stage is a simple planetary stage, the carrier may be provided with a flange extending around, and bearing mounted to, the common ring gear. To reduce weight and increase robustness, the planetary gears of a stage are retained on their carrier by a bumper ring provided between carriers. An angle sensor may be provided between the stationary and rotary housings.
摘要翻译：接头可以在固定壳体和旋转壳体之间具有多级行星齿轮箱。为了适应不同的齿轮比，旋转壳体可以通过可释放的附接件连接到固定壳体。这允许行星齿轮箱的部分被更换，使得例如最后一级可以选择为简单或复合差速行星级。为了允许不同的容量，阶段的太阳齿轮和齿圈的所有齿的总和与阶段的行星齿轮啮合到三号和四号的乘数产生一个整数。以这种方式，舞台可以设置有三个或四个行星齿轮。齿轮箱可以具有与多个简单行星级共同的齿圈。在最后一个阶段是简单的行星阶段的情况下，载体可以设置有围绕公共环形齿轮延伸并且轴承安装在普通齿圈上的凸缘。为了减轻重量并提高坚固性，通过设置在载体之间的保险杠将载物台的行星齿轮保持在其载体上。可以在固定和旋转壳体之间设置角度传感器。

59. 发明授权

US06594183B1 Wear leveling techniques for flash EEPROM systems 失效
公开(公告)号：US06594183B1
公开(公告)日：2003-07-15
申请号：US09108084
申请日：1998-06-30
申请人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
发明人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
IPC分类号： G11C1604
CPC分类号： G11C16/3495 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C8/12 , G11C16/349
摘要： A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

60. 发明授权

US06519691B2 Method of controlling a memory device by way of a system bus 有权
标题翻译：通过系统总线控制存储器件的方法
公开(公告)号：US06519691B2
公开(公告)日：2003-02-11
申请号：US09854343
申请日：2001-05-11
申请人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
发明人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
IPC分类号： G06F1200
CPC分类号： G06F12/0661 , G06F2212/2022
摘要： A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.
摘要翻译：具有存储器控制器，存储器单元阵列和存储器操作管理器的非易失性存储器系统。操作管理器通常通过系统总线从控制器接收到程序，读取和擦除指令后执行存储器程序，读取和擦除操作。在管理器中提供地址块电路，其能够根据由控制器确定的地址块电路的状态在单个地址或多个地址上执行存储器操作。可以基于由控制器提供的单个地址来生成多个地址，使得可以编程或读取存储器的扇区，从而简化存储器操作并减少存储器控制器的开销。

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