专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US4975757A Complementary semiconductor device 失效
标题翻译：互补半导体器件
公开(公告)号：US4975757A
公开(公告)日：1990-12-04
申请号：US111122
申请日：1987-10-20
申请人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
发明人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L21/823807 , H01L27/0928
摘要： A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

52. 发明授权

US4870615A Nonvolatile floating gate semiconductor memory device 失效
标题翻译：非易失性浮栅半导体存储器件
公开(公告)号：US4870615A
公开(公告)日：1989-09-26
申请号：US150290
申请日：1988-01-29
申请人： Tadashi Maruyama , Yukio Wada , Tomohisa Shigematsu , Yasoji Suzuki , Makoto Yoshizawa
发明人： Tadashi Maruyama , Yukio Wada , Tomohisa Shigematsu , Yasoji Suzuki , Makoto Yoshizawa
IPC分类号： G11C17/00 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0433
摘要： A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

53. 发明授权

US4529897A Analog switch device having threshold change reducing means 失效
标题翻译：具有阈值变化减小装置的模拟开关装置
公开(公告)号：US4529897A
公开(公告)日：1985-07-16
申请号：US398356
申请日：1982-07-15
申请人： Yasoji Suzuki , Kenji Matsuo , Akira Yamaguchi
发明人： Yasoji Suzuki , Kenji Matsuo , Akira Yamaguchi
IPC分类号： H03K17/687 , H03K3/01
CPC分类号： H03K17/6872 , H03K2217/0018
摘要： An analog switch device has p- and n-channel metal oxide semiconductor field effect transistors, each having a source electrode, a drain electrode, a gate electrode and a substrate electrode. The p- and n-channel metal oxide semiconductor field effect transistors are connected parallel to each other. First and second analog signals are received and produced at a pair of nodes between the p- and n-channel metal oxide semiconductor field effect transistors. Control signals which are inverted with each other are respectively supplied to the gate electrodes of the p- and n-channel metal oxide semiconductor field effect transistors. A voltage buffer circuit is provided for applying a predetermined voltage to the substrate electrode of one of the p- and n-channel metal oxide semiconductor field effect transistors so as to decrease a change in a threshold voltage due to the source-substrate bias effect.
摘要翻译：模拟开关装置具有p沟道金属氧化物半导体场效应晶体管和n沟道金属氧化物半导体场效应晶体管，每个具有源电极，漏电极，栅电极和衬底电极。 p沟道和n沟道金属氧化物半导体场效应晶体管彼此并联连接。第一和第二模拟信号在p沟道金属氧化物半导体场效应晶体管和n沟道金属氧化物半导体场效应晶体管之间的一对节点处被接收和产生。彼此反转的控制信号分别提供给p沟道金属氧化物半导体场效应晶体管和n沟道金属氧化物半导体场效应晶体管的栅电极。提供电压缓冲电路，用于向p沟道金属氧化物半导体场效应晶体管和n沟道金属氧化物半导体场效应晶体管之一的衬底电极施加预定电压，以便减小由于源极 - 衬底偏置效应引起的阈值电压的变化。

54. 发明授权

US4464587A Complementary IGFET Schmitt trigger logic circuit having a variable bias voltage logic gate section 失效
标题翻译：具有可变偏置电压逻辑门极部分的互补IGFET施密特触发逻辑电路
公开(公告)号：US4464587A
公开(公告)日：1984-08-07
申请号：US295825
申请日：1981-08-24
申请人： Yasoji Suzuki , Kenji Matsuo
发明人： Yasoji Suzuki , Kenji Matsuo
IPC分类号： H03K3/3565 , H03K3/037 , H03K3/356 , H03K19/094
CPC分类号： H03K3/3565
摘要： A logic gate section of a Schmitt trigger circuit has first and second nodes to which variable bias voltages are applied. A first bias control IGFET is connected between the first node and a first potential terminal. A second bias control IGFET is connected between the first node and a second potential terminal. A third bias control IGFET is connected between the second node and the first potential terminal. A fourth bias control IGFET is connected between the second node and the second potential terminal. A control signal to the gates of the first and fourth bias control IGFET's is provided by the Schmitt trigger input signal and the control signal to each of the gates of the third and fourth bias control IGFET's is provided by the Schmitt trigger feedback connection of two series-connected inverters.
摘要翻译：施密特触发电路的逻辑门极部分具有施加可变偏置电压的第一和第二节点。第一偏置控制IGFET连接在第一节点和第一电位端子之间。第一偏置控制IGFET连接在第一节点和第二电位端子之间。第三偏置控制IGFET连接在第二节点和第一电位端子之间。第四偏置控制IGFET连接在第二节点和第二电位端子之间。通过施密特触发输入信号提供到第一和第四偏置控制IGFET的栅极的控制信号，并且通过两个串联的施密特触发器反馈连接提供到第三和第四偏置控制IGFET的每个栅极的控制信号连接的逆变器。

55. 发明授权

US4439697A Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US4439697A
公开(公告)日：1984-03-27
申请号：US333321
申请日：1981-12-22
申请人： Yasoji Suzuki , Hiroaki Suzuki , Yukihiro Saeki
发明人： Yasoji Suzuki , Hiroaki Suzuki , Yukihiro Saeki
IPC分类号： G11C17/00 , G11C11/419 , G11C17/12 , G11C17/18 , H03K5/153 , G11C7/06 , H03K5/24
CPC分类号： G11C17/12
摘要： A sense amplifier circuit is disclosed in which a ROM is grouped into a plurality of ROM arrays and outputs from sense amplifiers provided for each ROM array are supplied to a single output terminal. In the sense amplifier circuit, each sense amplifier has a P-MOS FET connected between the output of the ROM array and a ground terminal and connected at the gate to a preset terminal, P-MOS FETs connected between the output of the ROM array and a positive power source and whose gates are respectively connected to the output terminal and a preset terminal, and an N MOS FET connected between the output terminal and the ground terminal and at the gate to the output terminal of the ROM array. Further, a P MOS FET is connected between the output terminal and the power source terminal and at the gate to an inverted preset terminal.
摘要翻译：公开了一种读出放大器电路，其中ROM被分组成多个ROM阵列，并且为每个ROM阵列提供的读出放大器的输出被提供给单个输出端。在感测放大器电路中，每个读出放大器具有连接在ROM阵列的输出端和接地端子之间的P-MOS FET，并且在门极连接到预置端子，连接在ROM阵列的输出端和正电源，其栅极分别连接到输出端子和预置端子，以及连接在输出端子和接地端子之间以及连接到ROM阵列的输出端子的栅极的N MOS FET。此外，P MOS FET连接在输出端子和电源端子之间，并且在栅极处连接到反相的预置端子。

56. 发明授权

US4389582A MOS Integrated logic circuit device with improved switching speed characteristics 失效
标题翻译： MOS集成逻辑电路器件具有改进的开关速度特性
公开(公告)号：US4389582A
公开(公告)日：1983-06-21
申请号：US116556
申请日：1980-01-29
申请人： Yasoji Suzuki , Kenji Matsuo
发明人： Yasoji Suzuki , Kenji Matsuo
IPC分类号： H03K19/017 , H03K19/096 , H03K19/20
CPC分类号： H03K19/01728 , H03K19/0963
摘要： A semiconductor integrated circuit device, which comprises:transistors constituting a plurality of series-connected logic circuits, wherein some of the mutually-facing or paired transistors of every two adjacent series-connected logic circuits or at least one pair thereof are so connected as to span said two adjacent circuits with a common gate provided between said paired transistors;conductors for connecting the source electrodes and/or the drain electrodes of said spanning paired transistors; anda plurality of signal generators for supplying required signals to the respective transistors, and whereby a MOS type logic circuit constructed by arranging those of the transistors which are supplied with a synchronizing signal closer to the output terminal than those of the transistors which are supplied with an input signal can be accelerated in operation.
摘要翻译：一种半导体集成电路器件，包括：构成多个串联逻辑电路的晶体管，其中每两个相邻的串联逻辑电路中的一些相互面对或成对的晶体管或至少一对串联的逻辑电路中的至少一对与跨越所述两个相邻电路，其中设置在所述成对晶体管之间的公共栅极; 用于连接所述跨越成对晶体管的源电极和/或漏电极的导体; 以及多个信号发生器，用于向各个晶体管提供所需的信号，并且由此通过将提供有比同时提供的同步信号的晶体管的晶体管的晶体管的晶体管的晶体管的晶体管的晶体管的晶体管的晶体管的晶体管可以在操作中加速输入信号。

57. 发明授权

US4233672A High-speed semiconductor device 失效
标题翻译：高速半导体器件
公开(公告)号：US4233672A
公开(公告)日：1980-11-11
申请号：US962222
申请日：1978-11-20
申请人： Yasoji Suzuki , Kiyofumi Ochii , Hirozi Asahi
发明人： Yasoji Suzuki , Kiyofumi Ochii , Hirozi Asahi
IPC分类号： G11C11/407 , G11C11/408 , G11C11/412 , H01L21/8244 , H01L27/02 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11 , H01L29/78 , G11C7/00
CPC分类号： H01L27/0222 , G11C11/412 , H01L27/0927 , H01L27/0218 , H01L27/105
摘要： A CMOS semiconductor memory device in which a memory cell array and peripheral circuits are formed on the same semiconductor substrate. Wells of the peripheral circuits with MOS transistors of one channel type formed therein are supplied with a PN junction reverse bias potential higher than that for wells of the memory cell array during the memory operation, while the potential at the peripheral circuit wells is made equal to the potential at the wells of the memory cell array when the memory is not operating. High-speed operation of the memory device may be achieved because the junction capacitance of the MOS transistors formed in the peripheral circuit wells is reduced when the memory is operating.
摘要翻译：一种其中存储单元阵列和外围电路形成在同一半导体衬底上的CMOS半导体存储器件。在存储器操作期间，其中形成有一个沟道类型的MOS晶体管的外围电路的阱被提供有比在存储器操作期间高于存储器单元阵列的阱的PN结反向偏压电位，而外围电路阱的电位等于当存储器不工作时，存储单元阵列的阱处的电位。可以实现存储器件的高速操作，因为当存储器工作时，外围电路阱中形成的MOS晶体管的结电容减小。

58. 发明授权

US4209797A Complementary semiconductor device 失效
标题翻译：互补半导体器件
公开(公告)号：US4209797A
公开(公告)日：1980-06-24
申请号：US922192
申请日：1978-07-05
申请人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
发明人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/788 , H01L29/792 , H01L27/02 , H01L29/04
CPC分类号： H01L21/823807 , H01L27/0928
摘要： A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. The N- and P-channel type silicon gate field effect transistors are formed in the P- and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
摘要翻译：互补半导体器件包括分别形成在半导体衬底中并具有基本上相同的杂质浓度的P型和N型半导体区域。 N沟道和P沟道型硅栅场效应晶体管分别形成在P沟道型和N沟道型区中。 P型和N沟道型硅栅场效应晶体管的栅电极由相同导电类型的多晶硅形成。相同导电类型的杂质被掺杂到两个半导体区域中以提供沟道掺杂区域。

59. 发明授权

US4143391A Integrated circuit device 失效
标题翻译：集成电路设备
公开(公告)号：US4143391A
公开(公告)日：1979-03-06
申请号：US917176
申请日：1978-06-20
申请人： Yasoji Suzuki , Tomohisa Shigematsu
发明人： Yasoji Suzuki , Tomohisa Shigematsu
IPC分类号： H01L27/092 , H01L27/02
CPC分类号： H01L27/0921
摘要： An integrated circuit device includes complementary MOS circuit elements formed in an N type semiconductor substrate with a P type region formed in the substrate. Protective circuit elements connected to an input terminal are formed in an area of the substrate other than the region thereof having the complementary MOS circuit elements formed therein. At least one of the regions constituting the protective circuit elements is formed in a P type additional region formed in the area of the N type substrate.

60. 发明授权

US4114192A Semiconductor memory device to reduce parasitic output capacitance 失效
标题翻译：半导体存储器件降低PARASITIC输出电容
公开(公告)号：US4114192A
公开(公告)日：1978-09-12
申请号：US777663
申请日：1977-03-15
申请人： Yasoji Suzuki , Kiyofumi Ochii
发明人： Yasoji Suzuki , Kiyofumi Ochii
IPC分类号： G11C11/401 , G11C11/409 , G11C11/412 , G11C11/419 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K3/356 , H03K19/096 , G11C7/06
CPC分类号： H03K19/0963 , G11C11/412 , G11C11/419 , H03K3/356
摘要： A semiconductor memory device includes a memory circuit formed of a plurality of matrix-arranged memory cells, a plurality of output data lines, each of which is connected to memory cells arranged in the same column of the matrix memory circuit, and a plurality of data-sensing circuits for delivering output data from the matrix memory circuit to an output device. The data-sensing circuits are divided into a plurality of groups, and the semiconductor memory device further comprises clocked inverters whose input terminals are connected to the output terminals of the respective groups of sensing circuits and whose output terminals are connected to the output device, and a control circuit which, when one of the data-sensing circuits issues an output, supplies an energizing signal to that of the clocked inverters which is connected to said one data-sensing circuit.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式