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51. 发明授权

US5995747A Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator 失效
标题翻译：三输入算术逻辑单元能够用移位器和/或掩码发生器执行所有可能的三个操作数布尔运算
公开(公告)号：US5995747A
公开(公告)日：1999-11-30
申请号：US794962
申请日：1997-02-04
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F7/52
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的布尔组合。算术逻辑单元能够形成三个输入的所有可能的布尔组合。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的N位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

52. 发明授权

US5696954A Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input 失效
标题翻译：三输入算术逻辑单元，其中一个输入处的移位装置形成两个输入的和/差逻辑地与第三输入进行逻辑运算，第三输入与和/差逻辑地与第三输入
公开(公告)号：US5696954A
公开(公告)日：1997-12-09
申请号：US486562
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F17/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。换档器可以是带有环绕的左滚筒旋转器或可控制的左/右移位器。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式为2N的第二输入信号，其中N是左移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

53. 发明授权

US5696913A Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
标题翻译：具有多个具有与每个处理器对应的统一地址空间的存储器的多处理系统中的唯一处理器标识符
公开(公告)号：US5696913A
公开(公告)日：1997-12-09
申请号：US472827
申请日：1995-06-07
申请人： Robert J. Gove , Karl Marion Guttag , Keith Balmer , Nicholas Kerin Ing-Simmons
发明人： Robert J. Gove , Karl Marion Guttag , Keith Balmer , Nicholas Kerin Ing-Simmons
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor. This enables programs which may execute independently of the processor within the multi-processing system.
摘要翻译：多处理系统包括多个存储器和多个处理器。每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。每个处理器具有预定的多个对应的存储器。这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。每个处理器具有一个具有唯一地识别多处理系统内的处理器的多个只读位的寄存器。处理器可以采用这种唯一的处理器标识符来计算对应于该处理器的基地址。这使得能够独立于多处理系统内的处理器执行的程序。

54. 发明授权

US5657036A Color display system with spatial light modulator(s) having color-to color variations for split reset 失效
标题翻译：具有空间光调制器的彩色显示系统，其具有用于分离复位的颜色到颜色变化
公开(公告)号：US5657036A
公开(公告)日：1997-08-12
申请号：US429388
申请日：1995-04-26
申请人： Vishal Markandey , Robert J. Gove
发明人： Vishal Markandey , Robert J. Gove
IPC分类号： G02B26/08 , G09G3/20 , G09G3/34 , H04N9/30 , H04N9/31
CPC分类号： G09G3/346 , G09G2310/0235 , G09G2320/0266 , G09G3/2022
摘要： A method of reducing artifacts in SLM-based display systems (10, 20), whose images are based on data displayed by bit-weight for pulse-width modulated intensity levels. The method can be used with a multiple spatial light modulators SLM system (20), which concurrently displays images of different colors, or with a single SLM system (10), which generates differently colored images sequentially during each frame period. For a multiple SLM system (20), the method is used with SLMs (14) that are memory-multiplexed, having "reset groups" that are loaded and displayed at different times. Corresponding rows of the SLM(s)s are associated with different reset groups.
摘要翻译：一种减少基于SLM的显示系统（10,20）中的伪像的方法，其图像基于通过位权重显示脉冲宽度调制强度级别的数据。该方法可以与同时显示不同颜色的图像的多空间光调制器SLM系统（20）一起使用，或者与单个SLM系统（10）一起使用，其在每个帧周期期间顺序地生成不同颜色的图像。对于多个SLM系统（20），该方法与被存储多路复用的SLM（14）一起使用，具有在不同时间加载和显示的“复位组”。 SLM的相应行与不同的重置组相关联。

55. 发明授权

US5638139A Motion adaptive scan-rate conversion using directional edge interpolation 失效
标题翻译：使用方向边缘插值的运动自适应扫描速率转换
公开(公告)号：US5638139A
公开(公告)日：1997-06-10
申请号：US475738
申请日：1995-06-07
申请人： Todd Clatanoff , Vishal Markandey , Robert J. Gove , Kazuhiro Ohara
发明人： Todd Clatanoff , Vishal Markandey , Robert J. Gove , Kazuhiro Ohara
IPC分类号： H04N7/01 , G06T7/20 , H04N5/44 , H04N5/91
CPC分类号： H04N7/012
摘要： A method for processing video data to produce a progressively scanned signal from an input of conventional interlaced video. The data is received at a processor (1), used to determine a motion signal (26) over time between field of the data. The motion signal is filtered to reduce errors caused by noise-corrupted video sources and then further filtered to spread out the determined motion signal. Edge information (30) is located and combined with the motion signal to produce an integrated progressive-scan signal (36) for display on a video display device, producing images with sharper edges and motion signals which have a lower susceptibility to noise.
摘要翻译：一种用于处理视频数据以从常规隔行视频的输入产生逐行扫描信号的方法。在处理器（1）处接收数据，用于随着时间在数据的场之间确定运动信号（26）。对运动信号进行滤波以减少由噪声损坏的视频源引起的误差，然后进一步滤波以扩展确定的运动信号。边缘信息（30）被定位并与运动信号组合以产生用于在视频显示设备上显示的集成逐行扫描信号（36），产生具有较低边缘的图像和对噪声具有较低敏感性的运动信号。

56. 发明授权

US5613146A Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors 失效
标题翻译：可重新配置的SIMD / MIMD处理器使用开关矩阵来允许多个处理器中的任何一个访问参数存储器
公开(公告)号：US5613146A
公开(公告)日：1997-03-18
申请号：US483658
申请日：1995-06-07
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F15/17375
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且处理器间通信链路允许处理器彼此通信以建立操作模式。通过交叉开关可访问的参数存储器与通信链路一起用于控制目的。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

57. 发明授权

US5524265A Architecture of transfer processor 失效
标题翻译：传输处理器架构
公开(公告)号：US5524265A
公开(公告)日：1996-06-04
申请号：US207503
申请日：1994-03-08
申请人： Keith Balmer , Robert J. Gove , Iain Robertson , Karl M. Guttag , Nicholas Ing-Simmons
发明人： Keith Balmer , Robert J. Gove , Iain Robertson , Karl M. Guttag , Nicholas Ing-Simmons
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： This invention is a data processor including a data transfer controller. The data transfer controller includes internal and external memory interfaces coupled to internal and external memory, respectively. A pipeline controller controls the internal memory interface and the external memory interface. A source address generator generates addresses for reading data. A destination address generator generates addresses for writing data. Buffer circuitry interposed between the source address generator and the destination address generator permits data to be aligned to differing source and destination data word sizes and differing data word boundaries. An external sequencer provides control signals for the external memory via the external memory interface. In the preferred embodiment, the buffer circuitry includes a first-in-first-out (FIFO) buffer having a plurality of registers. This permits continued operations in many cases when either the source or destination memory operations temporarily stall. The buffer circuitry preferably is used for buffering processor requested data transfers. Also a further cache buffer having a plurality of registers is used in buffering instruction cache service requests. The data transfer controller includes refresh registers coupled to the external sequencer. This provides data refreshing of dynamic random access memories. The data transfer controller further includes request prioritization circuitry coupled to the pipeline controller for prioritization of data transfer requests to the pipeline controller.
摘要翻译：本发明是一种包括数据传输控制器的数据处理器。数据传输控制器分别包括耦合到内部和外部存储器的内部和外部存储器接口。管道控制器控制内部存储器接口和外部存储器接口。源地址生成器生成用于读取数据的地址。目的地址生成器生成写入数据的地址。插入在源地址发生器和目的地地址发生器之间的缓冲电路允许数据与不同的源和目的数据字大小和不同的数据字边界对准。外部定序器通过外部存储器接口为外部存储器提供控制信号。在优选实施例中，缓冲电路包括具有多个寄存器的先进先出（FIFO）缓冲器。在许多情况下，当源或目标存储器操作暂时停止时，这允许持续的操作。缓冲电路优选地用于缓冲处理器所请求的数据传输。另外，在缓存指令高速缓存服务请求中使用具有多个寄存器的另外的高速缓存缓冲器。数据传输控制器包括耦合到外部定序器的刷新寄存器。这提供了动态随机存取存储器的数据刷新。数据传输控制器还包括耦合到流水线控制器的请求优先化电路，用于将流量控制器的数据传输请求优先化。

58. 发明授权

US5522083A Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors 失效
标题翻译：可重构的多处理器在SIMD模式下运行，一个处理器获取剩余处理器使用的指令
公开(公告)号：US5522083A
公开(公告)日：1996-05-28
申请号：US264111
申请日：1994-06-22
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F15/17375
摘要： There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路，并且处理器间通信链路允许处理器彼此通信以建立操作模式。通过交叉开关可访问的参数存储器与通信链路一起用于控制目的。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

59. 发明授权

US5493646A Pixel block transfer with transparency 失效
标题翻译：像素块传输透明度
公开(公告)号：US5493646A
公开(公告)日：1996-02-20
申请号：US208161
申请日：1994-03-08
申请人： Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
发明人： Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
IPC分类号： G06F13/28 , G09G5/393 , G06F12/00
CPC分类号： G06F13/28 , G09G5/393
摘要： A data processor with a transparency detection data transfer controller transfers data from a block of source addresses to a block of destination addresses. A transparency register stores transparency data. A comparator compares the recalled data to the stored transparency data and indicates whether the data to be transferred is to be written to the memory. The recalled data to be transferred is not to be written into the memory if it matches the transparency data. The transparency register may store a multiple of a multibit minimum amount of data to be transferred. The data to be transferred has a selected size which is an integral multiple of a minimum amount of data to be transferred. The comparator includes plural data comparators corresponding to each multibit minimum amount of data to be transferred. A multiplexer receives comparison signals and an indication of the selected data size and provides a number of indications of whether the data to be transferred is to be written to equal memory equal to the number of times the data words of the selected size fit within the transparency register. In the preferred embodiment the selected data size may be 8, 16, 32 or 64 bits and the transparency register stores 64 bits.
摘要翻译：具有透明度检测数据传输控制器的数据处理器将数据从源地址块传送到目的地址块。透明度寄存器存储透明度数据。比较器将调用的数据与存储的透明度数据进行比较，并指示要传送的数据是否要写入存储器。要转移的被调用数据如果与透明度数据匹配，则不会写入到存储器中。透明度寄存器可以存储要传送的多位最小数据量的倍数。要传送的数据具有选择的大小，其是要传送的最小数据量的整数倍。比较器包括对应于要传送的每个多位最小数据量的多个数据比较器。多路复用器接收比较信号和选择的数据大小的指示，并提供多个指示，以便将要传送的数据是否被写入相等的存储器，等于所选尺寸的数据字在透明度内的数量寄存器。在优选实施例中，所选择的数据大小可以是8,16,32或64位，并且透明度寄存器存储64位。

60. 发明授权

US5467138A Field to frame video pixel data generation 失效
标题翻译：帧到帧视频像素数据生成
公开(公告)号：US5467138A
公开(公告)日：1995-11-14
申请号：US412839
申请日：1995-03-29
申请人： Robert J. Gove
发明人： Robert J. Gove
IPC分类号： H04N5/74 , H04N5/14 , H04N5/44 , H04N7/01
CPC分类号： H04N7/012 , H04N5/144 , Y10S348/91
摘要： A pixel generator and method of generating pixel data for creating frames of video pixel data from fields of input video pixel data. The pixel processor 16 includes a field buffer circuit 36 that stores a plurality of fields of input video pixel data. Coupled to the field buffer are a feature detector 38 and a pixel generator 40. The feature detector 38 generates one or more feature magnitude signals based upon one or more of the fields of input video pixel data. The pixel generator 40 has at least two logic circuits for generating at least two different intermediate pixel data values based on the input pixel data. Coupled to feature detector 38 is feature analyzer 42 that selects a feature weight corresponding to each intermediate pixel data value, the weight being based upon the value of the feature magnitude signals. Coupled to feature analyzer 42 and pixel generator 40, is a pixel averager 44 that generates output pixel data based upon a weighted average of the intermediate pixel data values.
摘要翻译：一种像素生成器和从输入视频像素数据的场产生用于创建视频像素数据帧的像素数据的方法。像素处理器16包括存储输入视频像素数据的多个场的场缓冲器电路36。耦合到场缓冲器是特征检测器38和像素发生器40.特征检测器38基于输入视频像素数据的一个或多个场产生一个或多个特征幅度信号。像素生成器40具有至少两个逻辑电路，用于基于输入像素数据生成至少两个不同的中间像素数据值。耦合到特征检测器38的特征分析器42选择对应于每个中间像素数据值的特征权重，权重基于特征幅度信号的值。耦合到特征分析器42和像素生成器40的是像素平均器44，其基于中间像素数据值的加权平均生成输出像素数据。

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