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51. 发明授权

US5930642A Transistor with buried insulative layer beneath the channel region 失效
标题翻译：晶体管与通道区域之下的埋入绝缘层
公开(公告)号：US5930642A
公开(公告)日：1999-07-27
申请号：US871468
申请日：1997-06-09
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L21/762 , H01L29/786 , H01L29/24
CPC分类号： H01L29/78696 , H01L21/26533 , H01L21/266 , H01L21/76243 , H01L29/6659 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.
摘要翻译：公开了一种在沟道区下方具有埋入绝缘层的晶体管。与常规SIMOX不同，掩埋绝缘层在通道区域下方具有比源极和漏极的底表面更靠近衬底顶表面的顶表面。优选地，通过将氧注入到衬底中然后进行高温退火来形成掩埋绝缘层，使得注入的氧与衬底中的硅反应形成连续化学计量的二氧化硅层。有利地，掩埋绝缘层为通道区域提供扩散阻挡层和电隔离屏障。

52. 发明授权

US5923983A Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects 失效
标题翻译：集成电路栅极导体，其具有基本上抵抗热载流子效应的栅极电介质
公开(公告)号：US5923983A
公开(公告)日：1999-07-13
申请号：US771871
申请日：1996-12-23
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/28247 , H01L29/4983 , H01L29/6659
摘要： An integrated circuit is formed whereby transistor gate dielectrics are made less susceptible to hot carrier effects. Barrier atoms are inserted into critical areas to minimize trapping of hot carriers within the gate dielectric. Barrier atoms are incorporated into critical areas within the gate dielectric, primarily at the juncture between the gate dielectric and the overlying gate conductor and underlying substrate. The barrier atoms serve to eliminate bond opportunities of hot carriers injected from the drain area. The barrier atoms are presented by elevating the temperature of the integrated circuit being produced and the barrier-embodied gas surrounding the circuit. The elevated temperatures occur within either an RTA furnace or an oxidizing furnace. Significant is the incorporation of barrier atoms during a normal process flow, either during polysilicon oxidation and/or implant anneal. According to one embodiment, barrier atoms are incorporated after the LDD implant during times in which a polysilicon oxide is grown. According to a second embodiment, barrier atoms are incorporated after the source/drain implant and during anneal of those implant species. In yet another embodiment, barrier atoms are incorporated during each of the above steps.
摘要翻译：形成集成电路，由此使得晶体管栅极电介质不易受热载流子效应的影响。阻挡原子被插入关键区域以最小化栅极电介质中热载流子的捕获。栅极原子被并入到栅极电介质的关键区域中，主要在栅极电介质和上覆栅极导体和下面的衬底之间的接合处。势垒原子用于消除从漏极区域注入的热载流子的键合机会。通过提高所产生的集成电路的温度和围绕电路的屏障实施的气体来呈现阻挡原子。高温发生在RTA炉或氧化炉内。重要的是在正常工艺流程期间，在多晶硅氧化和/或注入退火期间引入势垒原子。根据一个实施方案，在生长多晶氧化物的时间内，在LDD注入之后结合势垒原子。根据第二实施例，在源极/漏极注入之后并且在那些植入物种的退火期间并入势垒原子。在另一个实施方案中，在上述每个步骤期间并入阻挡原子。

53. 发明授权

US5899732A Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device 失效
标题翻译：通过多晶硅栅极注入硅的方法，用于半导体器件的穿通控制
公开(公告)号：US5899732A
公开(公告)日：1999-05-04
申请号：US837937
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/225 , H01L21/265 , H01L21/322 , H01L21/336 , H01L21/8238 , H01L29/10
CPC分类号： H01L29/66492 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L21/3221 , H01L21/8238 , H01L29/1083 , H01L29/6659
摘要： A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.
摘要翻译：受损硅的区域被用作吸杂硅衬底中的杂质的吸杂区域。损坏的硅的区域在器件的栅极电极形成之后通过将硅原子注入到硅衬底中而在器件的源极和漏极区域之间形成。受损区域随后退火，并且在退火过程期间，诸如硼的掺杂剂原子偏析到该区域，局部地增加该区域中的掺杂剂浓度。先前损坏的区域位于确定设备穿透特性的位置。用于产生吸杂效应的硅植入物在栅极形成之后进行，使得紧邻在结点处的区域保持在较低掺杂剂浓度以减小结电容。将硅注入到多晶硅栅极附近以引发诸如硼或磷的掺杂剂原子的瞬态增强扩散（TED），以控制器件的穿透特性。在使用自对准吸气植入物在衬底上形成栅电极之后执行穿通控制植入。

54. 发明授权

US5888675A Reticle that compensates for radiation-induced lens error in a photolithographic system 失效
标题翻译：补偿光刻系统中辐射诱发的透镜误差的光罩
公开(公告)号：US5888675A
公开(公告)日：1999-03-30
申请号：US760031
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F1/00 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70433 , G03F1/70 , G03F7/70241
摘要： A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.
摘要翻译：掩模版提供图像图案并补偿光刻系统中的透镜误差。使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。可以通过调节辐射透射区域的构造（或布局）来结构地修改掩模版，例如通过调节石英基底的顶表面上的铬图案。或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

55. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

56. 发明授权

US5831306A Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region 失效
标题翻译：具有轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称晶体管
公开(公告)号：US5831306A
公开(公告)日：1998-11-03
申请号：US823946
申请日：1997-03-25
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835
摘要： An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
摘要翻译：公开了一种包括轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称IGFET。优选地，轻掺杂漏极区域和重掺杂源极区域提供通道结。制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以将轻掺杂源区域分成重掺杂源区，而不掺杂轻掺杂漏极区，分别与第一和第二侧壁相邻形成第一和第二间隔，并施加第三离子注入以将重掺杂源区的一部分转换到外部所述第一间隔物进入超重掺杂源区，而不掺杂所述第一间隔物下方的重掺杂源区的一部分，以及将所述第二间隔区外部的所述轻掺杂漏极区的一部分转换为重掺杂漏极区，而不掺杂第二间隔物下方的轻掺杂漏极区的部分。有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

57. 发明授权

US5445975A Semiconductor wafer with enhanced pre-process denudation and process-induced gettering 失效
标题翻译：半导体晶片具有增强的预处理剥蚀和工艺引起的吸气
公开(公告)号：US5445975A
公开(公告)日：1995-08-29
申请号：US206977
申请日：1994-03-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/322 , H01L21/324
CPC分类号： H01L21/3225 , Y10S148/06
摘要： A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.
摘要翻译：提供了一种用于预处理剥蚀和具有其中实施的具有一个或多个单片器件的CZ硅晶片的工艺诱导吸除的方法。在氢环境中进行预处理剥蚀以使氧扩散以及保持间隙硅熔剂远离衬底表面。在低温下进行过程诱导的吸气以确保堆垛层错，并且在栅极氧化之前的表面处的间隙硅键不会产生表面不规则性。涉及沉淀生长的剥蚀/吸除循环的第三步骤因此被延迟或预防，直到场氧化物生长。在多晶硅沉积之后发生的衬底表面内或附近的氧和/或间隙硅中的任何变化或移动对所建立的栅极氧化物的影响最小。因此，通过本方法增强栅极氧化物完整性（例如，击穿电压和均匀性）。

58. 发明授权

US06661057B1 Tri-level segmented control transistor and fabrication method 失效
标题翻译：三电平分段控制晶体管及其制造方法
公开(公告)号：US06661057B1
公开(公告)日：2003-12-09
申请号：US09056836
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L27088
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/32053 , H01L21/76802 , H01L21/76855 , H01L29/66484 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7833 , Y10S257/90
摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
摘要翻译：晶体管形成在具有分段栅极结构的有源区中。分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。这些间隔物通过绝缘层与栅电极电隔离。形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

59. 发明授权

US06410409B1 Implanted barrier layer for retarding upward diffusion of substrate dopant 失效
标题翻译：用于延缓衬底掺杂剂的向上扩散的植入阻挡层
公开(公告)号：US06410409B1
公开(公告)日：2002-06-25
申请号：US08741799
申请日：1996-10-31
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21265
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/26513 , H01L21/74
摘要： Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.
摘要翻译：在随后的热处理操作（例如退火）期间，在半导体衬底内形成深P +层的硼向上扩散。用于延迟硼的这种向上扩散的方法包括注入氮以在P +层的上边界附近形成氮阻挡层，并且远低于晶体管源/漏区。一个实施例包括形成在下面的P +衬底上的轻掺杂的外延层。在另一个实施例中，深硼注入在P-衬底内形成P +层，并提供外延层的许多优点，而不需要这样的外延层。以1-3MeV的优选能量进行氮注入，以在1-5微米范围内的深度形成注入的氮阻挡层。氧也可以被植入以形成扩散阻挡层，以阻止形成深N +层的砷或磷的向上扩散。

60. 发明授权

US06380055B2 Dopant diffusion-retarding barrier region formed within polysilicon gate layer 有权
标题翻译：在多晶硅栅极层内形成的掺杂扩散阻滞层
公开(公告)号：US06380055B2
公开(公告)日：2002-04-30
申请号：US09177043
申请日：1998-10-22
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L213205
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/32155
摘要： A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 Å thick. Any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness of approximately 25-60 Å, when using a p-type dopant, such as boron.
摘要翻译：扩散阻滞屏障区域被结合到栅电极中以减少掺杂剂朝向栅极电介质的向下扩散。阻挡区域是在两个单独形成的多晶硅层之间形成的含氮扩散阻滞区域。多晶硅的上层比多晶硅的下层掺杂更多，并且势垒区域用于将大部分掺杂剂保持在多晶硅的上层内，并且还可以允许一些掺杂剂扩散到多晶硅的下层。阻挡区域可以例如通过在含氮环境中退火第一多晶硅层以在第一多晶硅层的顶表面处形成氮化层而形成。可以通过在第一多晶硅层的顶表面上沉积含氮层，例如氮化硅或氮化钛层来形成阻挡区。含氮层的厚度优选为约5〜约厚。驻留在栅极电介质顶部的任何氮可以保持在小于约2％的浓度。当使用诸如硼的p型掺杂剂时，本发明特别适用于薄栅极电介质，例如厚度大约为25埃的那些。

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