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    • 51. 发明申请
    • Nonvolatile memory utilizing hot-carrier effect with data reversal function
    • 使用具有数据反转功能的热载波效应的非易失性存储器
    • US20080186767A1
    • 2008-08-07
    • US11701958
    • 2007-02-02
    • Takashi KikuchiKenji Noda
    • Takashi KikuchiKenji Noda
    • G11C16/06
    • G11C14/00G11C14/0063
    • A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.
    • 非易失性半导体存储器件包括控制电路,反相电路和存储器单元,每个存储器单元包括具有第一节点和第二节点的锁存器,板线,具有源/漏节点之一的第一MIS晶体管 耦合到锁存器的第一节点,耦合到板线的源极/漏极节点中的另一个以及耦合到字线的栅极节点以及耦合到第二节点的源极/漏极节点之一的第二MIS晶体管 耦合到板线的源/漏节点中的另一个和耦合到字线的栅极节点,其中控制电路被配置为通过从锁存器读取数据来反转锁存在锁存器中的数据, 使反相电路反转读取的数据,并将反相数据写入锁存器。
    • 54. 发明授权
    • Composite construction
    • 复合建筑
    • US07229691B2
    • 2007-06-12
    • US10781298
    • 2004-02-18
    • Kenji Noda
    • Kenji Noda
    • B22F3/00B32B9/00
    • B22F1/004B22F1/025B22F2005/001B22F2998/00B22F2998/10C22C47/04C22C47/068C22C49/14Y10T428/2991Y10T428/30C22C26/00C22C47/20
    • The composite structure of the present invention comprises an elongate core material of a sintered diamond material comprising 80% by volume or more diamond particles of a mean particle size not larger than 3.5 μm that are bound by an iron group metal; and a shell layer of a sintered alloy comprising at least one kind of hard particles selected from among carbide, nitride and carbonitride of at least one metal element selected from the group of 4a, 5a and 6a group metals of the Periodic Table and diamond particles having a mean particle size not larger than 5 μm that are bound by an iron group metal, wherein content of the diamond particles in the shell layer is from 5 to 45% by volume, thereby improving wear resistance, adhesion resistance and chipping resistance of cutting tool, while maintaining high hardness and high strength.
    • 本发明的复合结构包括由铁族金属结合的包含80体积%或更多的平均粒度不大于3.5μm的金刚石颗粒的烧结金刚石材料的细长芯材料; 以及烧结合金的壳层,其包含选自元素周期表中的4a,5a和6a族金属中的至少一种金属元素的碳化物,氮化物和碳氮化物中的至少一种硬颗粒和具有 由铁族金属结合的不大于5μm的平均粒径,其中壳层中的金刚石颗粒的含量为5〜45体积%,从而提高切削工具的耐磨性,耐粘连性和耐崩裂性 同时保持高硬度和高强度。
    • 56. 发明申请
    • Photomask and method for forming pattern
    • 光掩模和形成图案的方法
    • US20050074682A1
    • 2005-04-07
    • US10957599
    • 2004-10-05
    • Kenji NodaShin Hashimoto
    • Kenji NodaShin Hashimoto
    • G03F7/00G03C5/00G03F1/08G03F1/14G03F7/20
    • G03F1/36
    • A photomask includes, on a translucent substrate, three or more first light-shielding portions each in insular shape having a property of shielding exposure light and spaced equidistantly, a second light-shielding portion having a property of shielding the exposure light and formed to connect the adjacent first light-shielding portions, and first light-transmitting portions each in slit shape having a property of transmitting the exposure light and formed to be surrounded with the first and second light-shielding portions. The second light-shielding portion is formed to contain a point located equidistantly from the three or more first light-shielding portions.
    • 一种光掩模在透光性基板上具有三个以上的具有隔离曝光光等间隔的特性的具有岛状的三个以上的第一遮光部,具有屏蔽曝光光的特性的第二遮光部,形成为连接 相邻的第一遮光部和具有透射曝光光的特性的狭缝状的第一透光部,形成为被第一和第二遮光部包围。 第二遮光部形成为包含与三个以上的第一遮光部等距离地设置的点。
    • 60. 发明申请
    • MIS-TRANSISTOR-BASED NONVOLATILE MEMORY FOR MULTILEVEL DATA STORAGE
    • 基于MIS-TRANSISTOR的非易失性存储器,用于多种数据存储
    • US20090310428A1
    • 2009-12-17
    • US12139550
    • 2008-06-16
    • Tadahiko HoriuchiKenji Noda
    • Tadahiko HoriuchiKenji Noda
    • G11C7/00
    • G11C11/5671G11C2211/5642G11C2211/5647
    • A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.
    • 存储器电路包括具有第一节点和第二节点的锁存器,用于存储数据,使得第一节点的逻辑电平为第二节点的逻辑电平的倒数,具有门节点的MIS晶体管,第一源极/ 漏极节点和第二源极/漏极节点,耦合到锁存器的第一节点的第一源极/漏极节点以及控制电路,被配置为控制MIS晶体管的栅极节点和第二源极/漏极节点向上 响应于存储在锁存器中的数据,在第一操作中MIS晶体管的阈值电压的持续变化,并且响应于存储在锁存器中的数据,在第二操作中使阈值电压下降。