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51. 发明授权

US07272047B2 Wordline voltage generating circuit including a voltage dividing circuit for reducing effects of parasitic capacitance 有权
标题翻译：字线电压产生电路包括用于减小寄生电容的影响的分压电路
公开(公告)号：US07272047B2
公开(公告)日：2007-09-18
申请号：US11177842
申请日：2005-07-08
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04 , G11C7/00
CPC分类号： G11C8/08
摘要： Disclosed is a voltage dividing circuit reducing effects of a parasitic capacitance and a wordline voltage generating circuit including that. The voltage dividing circuit according to an aspect of the present invention includes a first resistor, a plurality of second resistors, and a selection means. The first resistor is connected between an output voltage node and a dividing voltage node. The plurality of second resistors are connectable between the dividing voltage node and a ground. The second resistors are sequentially selected in response to a step control signal and connected to ground. In order to reduce the sum of a parasitic capacitance existing in the second resistors, the resistors are arranged in groups, and the selection means connects only that group that contains a selected resistor to the dividing voltage node.
摘要翻译：公开了一种降低寄生电容的影响的分压电路和包括其的字线电压发生电路。根据本发明的一个方面的分压电路包括第一电阻器，多个第二电阻器和选择装置。第一个电阻连接在输出电压节点和分压电压节点之间。多个第二电阻器可以在分压电压节点和地之间连接。第二电阻器响应于步进控制信号被顺序选择并连接到地。为了减少存在于第二电阻器中的寄生电容的总和，电阻器被分组布置，并且选择装置仅将包含所选电阻器的组件连接到分压电压节点。

52. 发明申请

US20070146052A1 Charge pump 审中-公开
标题翻译：电荷泵
公开(公告)号：US20070146052A1
公开(公告)日：2007-06-28
申请号：US11489476
申请日：2006-07-20
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump is disclosed. The charge pump comprises a plurality of first voltage boosting circuits (VBCs), each comprising a first output node and a precharge circuit adapted to precharge the first output node, and at least one second VBC connected in series with the plurality of first VBCs, wherein each of the at least one second VBC does not comprise any precharge circuit.
摘要翻译：公开了电荷泵。电荷泵包括多个第一升压电路（VBC），每个包括第一输出节点和适于对第一输出节点预充电的预充电电路以及与多个第一VBC串联连接的至少一个第二VBC，其中所述至少一个第二VBC中的每一个不包括任何预充电电路。

53. 发明授权

US07190618B2 Semiconductor device for reducing coupling noise 有权
标题翻译：用于减少耦合噪声的半导体器件
公开(公告)号：US07190618B2
公开(公告)日：2007-03-13
申请号：US10915555
申请日：2004-08-11
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C16/26
摘要： Semiconductor devices, semiconductor memory device, or flash memories including a high voltage region including high voltage elements, a low voltage region including low voltage elements, and a switch transistor, such as a low voltage switch transistor, connecting the high voltage region and the high voltage region. The switch transistor reduces or eliminates coupling noise between sense nodes without increasing chip area.
摘要翻译：半导体器件，半导体存储器件或闪存，其包括包括高电压元件的高电压区域，包括低电压元件的低电压区域，以及连接高电压区域和高电压区域的诸如低压开关晶体管的开关晶体管电压区域。开关晶体管减少或消除感测节点之间的耦合噪声，而不增加芯片面积。

54. 发明授权

US07158418B2 Non-volatile memory device capable of changing increment of program voltage to mode of operation 有权
标题翻译：能够将编程电压增加到操作模式的非易失性存储器件
公开(公告)号：US07158418B2
公开(公告)日：2007-01-02
申请号：US10976383
申请日：2004-10-29
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/04 , G11C16/3454 , G11C16/3459 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/1202
摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment of the word line voltage is varied according to the mode of operation, namely, a test mode or normal mode. Thus test time can be shortened.
摘要翻译：非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给所选行的字线电压;以及程序控制器，用于产生步进控制信号，使得字的增量线路电压根据操作模式，即测试模式或正常模式而变化。因此可以缩短测试时间。

55. 发明授权

US07154789B2 High-voltage generator circuit and semiconductor memory device including the same 有权
标题翻译：高压发生器电路和包括其的半导体存储器件
公开(公告)号：US07154789B2
公开(公告)日：2006-12-26
申请号：US10977426
申请日：2004-10-28
申请人： Jong-Hwa Kim , Dae-Seok Byeon
发明人： Jong-Hwa Kim , Dae-Seok Byeon
IPC分类号： G11C5/14
CPC分类号： H02M3/073 , H02M2001/0041
摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.
摘要翻译：根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。分压器通过分压高电压在输出节点产生分压。放电部分响应于第一控制信号将高电压放电到电源电压。比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。

56. 发明申请

US20060274578A1 NAND flash memory device having page buffer adapted to discharge bit line voltage during erase operation 失效
标题翻译：具有适于在擦除操作期间放电位线电压的页缓冲器的NAND闪存器件
公开(公告)号：US20060274578A1
公开(公告)日：2006-12-07
申请号：US11443205
申请日：2006-05-31
申请人： Pan-Suk Kwak , Dae-Seok Byeon
发明人： Pan-Suk Kwak , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/16
摘要： A NAND flash memory device comprises a memory cell array comprising a plurality of memory cells, a plurality of page buffers, and an isolation circuit connected between the memory cell array and the plurality of page buffers. The isolation circuit comprises a high voltage transistor adapted to disconnect a first bit line connected to the memory cell array from a second bit line connected to the one of the page buffers during an erase operation of the NAND flash memory device. During the read operation, a third bit line arranged in parallel with the second bit line and connected to one of the page buffers is discharged to prevent the page buffer from being damaged due to coupling capacitance between the second and third bit lines.
摘要翻译： NAND闪速存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，多个页缓冲器以及连接在存储单元阵列与多个页缓冲器之间的隔离电路。隔离电路包括高电压晶体管，其适于在NAND闪速存储器件的擦除操作期间将连接到存储单元阵列的第一位线与连接到该页缓冲器之一的第二位线断开。在读取操作期间，放电与第二位线并联并连接到页面缓冲器之一的第三位线，以防止页缓冲器由于第二位线和第三位线之间的耦合电容而损坏。

57. 发明申请

US20060092703A1 Flash memory device and method of programming the same 有权
标题翻译：闪存设备及其编程方法相同
公开(公告)号：US20060092703A1
公开(公告)日：2006-05-04
申请号：US11205245
申请日：2005-08-16
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08
摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.
摘要翻译：闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。提供字线驱动程序以提高编程效率。字线驱动器通过多个字线电耦合到存储器阵列。字线驱动器包括多个通过电压开关。这些开关具有由二极管电耦合到多个字线的输出。编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

58. 发明授权

US07038949B2 Non-volatile memory device capable of changing increment of program voltage according to mode of operation 有权
标题翻译：能够根据操作模式改变编程电压增量的非易失性存储器件
公开(公告)号：US07038949B2
公开(公告)日：2006-05-02
申请号：US10957307
申请日：2004-09-30
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals and a program controller for sequentially activating the step control signals during a program cycle. During the program cycle, the word line voltage generator circuit controls the increment of the word line voltage differently according to the mode of operation, namely, a test mode or a normal mode. Thus test time can be shortened.
摘要翻译：非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给选定行的字线电压;以及程序控制器，用于在编程周期期间顺序激活步进控制信号。在编程周期中，字线电压发生器电路根据操作模式，即测试模式或正常模式，不同地控制字线电压的增量。因此可以缩短测试时间。

59. 发明授权

US06888756B2 Low-voltage non-volatile semiconductor memory device 有权
标题翻译：低压非易失性半导体存储器件
公开(公告)号：US06888756B2
公开(公告)日：2005-05-03
申请号：US10376615
申请日：2003-02-28
申请人： Dae-Seok Byeon , June Lee , Gyung-Han Lee
发明人： Dae-Seok Byeon , June Lee , Gyung-Han Lee
IPC分类号： G11C16/06 , G11C5/14 , G11C16/02 , G11C16/24 , G11C16/30 , G11C16/04
CPC分类号： G11C5/147 , G11C16/24 , G11C16/30
摘要： The disclosure is a non-volatile semiconductor memory device including a bias circuit that generates a bias voltage for controlling an NMOS transistor connected to both a bit line and a page buffer circuit. The bias circuit generates a first voltage, which is greater than a power source voltage, as the bias signal in a precharge period of a read operation. The bias circuit also generates a second voltage, which is less than the power source voltage, as the bias signal in a sensing period of the read operation.
摘要翻译：本公开是一种非易失性半导体存储器件，包括偏置电路，该偏置电路产生用于控制连接到位线和页缓冲器电路的NMOS晶体管的偏置电压。偏置电路在读取操作的预充电时段中产生大于电源电压的第一电压作为偏置信号。偏置电路还在读取操作的感测周期中产生小于电源电压的第二电压作为偏置信号。

60. 发明授权

US09851912B2 Memory device, memory system and method of operating memory device 有权
公开(公告)号：US09851912B2
公开(公告)日：2017-12-26
申请号：US15443647
申请日：2017-02-27
申请人： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
发明人： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
IPC分类号： G11C11/34 , G11C16/04 , G06F3/06
CPC分类号： G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
摘要： A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

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