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51. 发明授权

US07112483B2 Method for forming a device having multiple silicide types 有权
标题翻译：用于形成具有多种硅化物类型的器件的方法
公开(公告)号：US07112483B2
公开(公告)日：2006-09-26
申请号：US10831021
申请日：2004-04-23
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

52. 发明申请

US20050170594A1 Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof 有权
标题翻译：具有晶格失配区的应变通道晶体管结构及其制造方法
公开(公告)号：US20050170594A1
公开(公告)日：2005-08-04
申请号：US11093847
申请日：2005-03-30
申请人： Yee-Chia Yeo , Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu
发明人： Yee-Chia Yeo , Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/06
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/165 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7842 , H01L29/7848
摘要： A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.
摘要翻译：具有晶格失配区的应变通道晶体管结构及其制造方法。晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，该区域和漏极区域包括具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

53. 发明授权

US06921913B2 Strained-channel transistor structure with lattice-mismatched zone 有权
标题翻译：具有晶格失配区的应变通道晶体管结构
公开(公告)号：US06921913B2
公开(公告)日：2005-07-26
申请号：US10379033
申请日：2003-03-04
申请人： Yee-Chia Yeo , Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu
发明人： Yee-Chia Yeo , Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/06
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/165 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7842 , H01L29/7848
摘要： A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.
摘要翻译：具有晶格失配区的应变通道晶体管结构及其制造方法。晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

54. 发明申请

US20050045949A1 Ultra-thin body transistor with recessed silicide contacts 审中-公开
标题翻译：具有凹陷硅化物触点的超薄体晶体管
公开(公告)号：US20050045949A1
公开(公告)日：2005-03-03
申请号：US10650445
申请日：2003-08-28
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L29/45 , H01L29/68 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/66636 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).
摘要翻译：一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210）（240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

55. 发明授权

US07851276B2 Methods and structures for planar and multiple-gate transistors formed on SOI 有权
标题翻译：在SOI上形成的平面和多栅极晶体管的方法和结构
公开(公告)号：US07851276B2
公开(公告)日：2010-12-14
申请号：US11676480
申请日：2007-02-19
申请人： Fu-Liang Yang , Yee-Chia Yeo , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/00 , H01L21/48
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.
摘要翻译：半导体器件包括绝缘体层，半导体层，第一晶体管和第二晶体管。半导体层覆盖绝缘体层。半导体层的第一部分具有第一厚度。半导体层的第二部分具有第二厚度。第二厚度大于第一厚度。第一晶体管具有由半导体层的第一部分形成的第一有源区。第二晶体管具有由半导体层的第二部分形成的第二有源区。第一晶体管可以是平面晶体管，例如，第二晶体管可以是多栅极晶体管。

56. 发明申请

US20100176424A1 Doping of Semiconductor Fin Devices 有权
标题翻译：半导体鳍片器件的掺杂
公开(公告)号：US20100176424A1
公开(公告)日：2010-07-15
申请号：US12732011
申请日：2010-03-25
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/786 , H01L29/04
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

57. 发明授权

US07701008B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US07701008B2
公开(公告)日：2010-04-20
申请号：US11446890
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

58. 发明授权

US07423323B2 Semiconductor device with raised segment 有权
标题翻译：具有凸起部分的半导体器件
公开(公告)号：US07423323B2
公开(公告)日：2008-09-09
申请号：US11064489
申请日：2005-02-23
申请人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/78684
摘要： A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.
摘要翻译：具有凸起部分的装置及其制造方法。提供SOI晶片，其具有衬底，设置在衬底上的绝缘层和设置在绝缘层上的半导体材料层。图案化半导体材料以形成台面结构。将晶片退火以在台面结构上形成凸起的段。

59. 发明授权

US07312136B2 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance 有权
标题翻译：制造具有应变通道层的晶片以提高电子和空穴迁移率以提高器件性能的方法
公开(公告)号：US07312136B2
公开(公告)日：2007-12-25
申请号：US10899270
申请日：2004-07-26
申请人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/20
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/324 , H01L21/76259 , H01L29/1054
摘要： A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
摘要翻译：实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。该方法在种子晶片上形成多孔硅层。使用H 2 H 2退火在多孔硅上形成光滑表面。沉积无应变的（松弛的）外延的Si 1 x 1-x层，并形成结合层。然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的Si 1 x 1-x x上的多孔Si层的部分。然后将手柄晶片在H 2 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

60. 发明授权

US07176092B2 Gate electrode for a semiconductor fin device 有权
标题翻译：用于半导体鳍片器件的栅电极
公开(公告)号：US07176092B2
公开(公告)日：2007-02-13
申请号：US10825872
申请日：2004-04-16
申请人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
摘要翻译：用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

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