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51. 发明授权

US07071052B2 Resistor with reduced leakage 有权
标题翻译：电阻泄漏减少
公开(公告)号：US07071052B2
公开(公告)日：2006-07-04
申请号：US10667871
申请日：2003-09-22
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/8249
CPC分类号： H01L27/1203 , H01L28/20
摘要： A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.
摘要翻译：电阻器100形成在半导体层106中，例如SOI衬底上的硅层。体区108形成在半导体层106的一部分中并被掺杂到第一导电类型（例如，n型或p型）。也在第一导电类型上掺杂的第一接触区域110形成在与身体区域108相邻的半导体层106中。第二接触区域112也形成在半导体层106中并且通过主体区域108与第一接触区域110间隔开。电介质层116覆盖在主体区域上并且由相对介电常数大于约8的材料形成。电极114覆盖电介质116。

52. 发明授权

US07052964B2 Strained channel transistor and methods of manufacture 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US07052964B2
公开(公告)日：2006-05-30
申请号：US11081919
申请日：2005-03-16
申请人： Yee-Chia Yeo , Chih-Hsin Ko , Wen-Chin Lee , Chenming Hu
发明人： Yee-Chia Yeo , Chih-Hsin Ko , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/76229 , H01L21/76237 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.
摘要翻译：半导体器件包括其中形成有第一和第二隔离沟槽的半导体材料区域。第一隔离槽衬有具有低氧扩散速率的第一材料并填充绝缘材料。第二隔离槽不是衬有第一材料，而是用绝缘材料填充。形成在第一隔离区域附近的第一晶体管和与第二隔离区域相邻形成的第二晶体管。

53. 发明申请

US20060081875A1 Transistor with a strained region and method of manufacture 有权
标题翻译：具有应变区域的晶体管及其制造方法
公开(公告)号：US20060081875A1
公开(公告)日：2006-04-20
申请号：US10967917
申请日：2004-10-18
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L31/109 , H01L31/0328 , H01L29/76
CPC分类号： H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/802
摘要： A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.
摘要翻译：晶体管结构包括覆盖衬底区域的沟道区域。衬底区域包括具有第一晶格常数的第一半导体材料。沟道区域包括具有第二晶格常数的第二半导体材料。源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

54. 发明授权

US06974755B2 Isolation structure with nitrogen-containing liner and methods of manufacture 失效
标题翻译：含氮衬垫的隔离结构及其制造方法
公开(公告)号：US06974755B2
公开(公告)日：2005-12-13
申请号：US10687377
申请日：2003-10-16
申请人： Chih-Hsin Ko , Yee-Chia Yeo , Chung-Hu Ge , Wen-Chin Lee
发明人： Chih-Hsin Ko , Yee-Chia Yeo , Chung-Hu Ge , Wen-Chin Lee
IPC分类号： H01L21/28 , H01L21/306 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L29/78
CPC分类号： H01L21/28123 , H01L21/76232 , H01L21/823481 , H01L29/7833
摘要： A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.
摘要翻译：半导体隔离沟槽包括衬底和形成在其中的沟槽。沟槽衬有含氮衬里并填充介电材料。优选地，所述含氮衬垫接触位于所述沟槽附近的诸如晶体管的器件的有源区。

55. 发明申请

US20050272188A1 Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
标题翻译：应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升
公开(公告)号：US20050272188A1
公开(公告)日：2005-12-08
申请号：US11201990
申请日：2005-08-11
申请人： Yee-Chia Yeo , Chun-Chieh Lin , Fu-Liang Yang , Mong-Song Liang , Chenming Hu
发明人： Yee-Chia Yeo , Chun-Chieh Lin , Fu-Liang Yang , Mong-Song Liang , Chenming Hu
IPC分类号： H01L21/00 , H01L21/84 , H01L27/12 , H01L31/109
CPC分类号： H01L29/1054 , H01L21/84 , H01L27/1203
摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.
摘要翻译：已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中电子迁移率。相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

56. 发明申请

US20050233525A1 Gate electrode for a semiconductor fin device 有权
标题翻译：用于半导体鳍片器件的栅电极
公开(公告)号：US20050233525A1
公开(公告)日：2005-10-20
申请号：US10825872
申请日：2004-04-16
申请人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.
摘要翻译：用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。栅极电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以跟随掺杂剂杂质的引入和激活。在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

57. 发明申请

US20050224907A1 Isolation structure with nitrogen-containing liner and methods of manufacture 审中-公开
公开(公告)号：US20050224907A1
公开(公告)日：2005-10-13
申请号：US11146661
申请日：2005-06-07
申请人： Chih-Hsin Ko , Yee-Chia Yeo , Chung-Hu Ke , Wen-Chin Lee
发明人： Chih-Hsin Ko , Yee-Chia Yeo , Chung-Hu Ke , Wen-Chin Lee
IPC分类号： H01L21/28 , H01L21/306 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L29/78
CPC分类号： H01L21/28123 , H01L21/76232 , H01L21/823481 , H01L29/7833
摘要： A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

58. 发明授权

US06949769B2 Suppression of MOSFET gate leakage current 有权
标题翻译：抑制MOSFET栅极漏电流
公开(公告)号：US06949769B2
公开(公告)日：2005-09-27
申请号：US10958472
申请日：2004-10-04
申请人： Chenming Hu , Yee-Chia Yeo
发明人： Chenming Hu , Yee-Chia Yeo
IPC分类号： H01L29/49 , H01L29/78 , H01L31/0256
CPC分类号： H01L29/78 , H01L29/49
摘要： A MOSFET has greatly reduced leakage current between the gate electrode and the channel, source and drain regions. The gate electrode materials have lower electron affinities than the channel, source and drain regions. Gate electrode materials with negative electron affinities can also be used. The use of these gate electrode materials enables the band structures of the gate electrode and the other regions to be aligned in a manner that eliminates tunneling states for carriers tunneling between the gate and the body of the device.
摘要翻译： MOSFET大大减少了栅极电极和沟道，源极和漏极区域之间的漏电流。栅电极材料具有比沟道，源极和漏极区更低的电子亲和力。也可以使用具有负电子亲和力的栅电极材料。使用这些栅极电极材料能够使栅电极和其它区域的带结构以排除隧道状态的方式排列，以便在器件的栅极和主体之间隧穿。

59. 发明授权

US06936881B2 Capacitor that includes high permittivity capacitor dielectric 有权
公开(公告)号：US06936881B2
公开(公告)日：2005-08-30
申请号：US10628020
申请日：2003-07-25
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01G4/228 , H01L21/00 , H01L21/02 , H01L21/334 , H01L21/762 , H01L21/8239 , H01L21/84 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/92 , H01L29/94
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

60. 发明申请

US20050156208A1 Device having multiple silicide types and a method for its fabrication 审中-公开
标题翻译：具有多种硅化物类型的器件及其制造方法
公开(公告)号：US20050156208A1
公开(公告)日：2005-07-21
申请号：US10955349
申请日：2004-09-30
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/76
CPC分类号： H01L29/665 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/785
摘要： Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.
摘要翻译：提供半导体器件及其制造方法。在一个示例中，半导体器件包括使用第一硅化物类型形成在衬底上的有源区和使用另一种硅化物类型形成在衬底上的另一有源区。两种硅化物类型不同，并且两种硅化物中的至少一种是合金硅化物。蚀刻停止层可覆盖至少一个硅化物区域。

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