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51. 发明申请

US20060170053A1 Accumulation mode multiple gate transistor 审中-公开
标题翻译：累积模式多栅晶体管
公开(公告)号：US20060170053A1
公开(公告)日：2006-08-03
申请号：US10434618
申请日：2003-05-09
申请人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/78618 , H01L2029/7857
摘要： A transistor (1) having, a fin (2) and a gate electrode (3) extending on more than one side of the fin (2) to comprise more than one gate (9) of the transistor (1), and a dopant in each of a source (6), drain (7) and a channel region (8), comprising a single dopant type.
摘要翻译：一种晶体管（1），具有在鳍片（2）的多于一侧上延伸以包括晶体管（1）的多于一个栅极（9）的翅片（2）和栅电极（3），以及掺杂剂在源（6），漏极（7）和沟道区（8）的每一个中，包括单一掺杂剂类型。

52. 发明申请

US20060084244A1 Silicon-on-insulator chip with multiple crystal orientations 有权
标题翻译：具有多个晶体取向的绝缘体上硅芯片
公开(公告)号：US20060084244A1
公开(公告)日：2006-04-20
申请号：US11073911
申请日：2005-03-07
申请人： Yee-Chia Yeo , Fu-Liang Yang
发明人： Yee-Chia Yeo , Fu-Liang Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L21/84
摘要： A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.
摘要翻译：绝缘体上硅芯片包括通常形成在衬底上的绝缘体层。具有第一晶体取向表面的第一硅岛覆盖绝缘体层，具有第二晶体取向表面的第二硅岛也覆盖在绝缘体层上。在一个实施例中，绝缘体上硅芯片还包括形成在第一硅岛上的第一导电类型的第一晶体管和形成在第二硅岛上的第二导电类型的第二晶体管。例如，当第一晶体管是p沟道晶体管时，第一晶体取向可以是（110），并且第二晶体取向可以是（100），而第二晶体管是n沟道晶体管。

53. 发明申请

US20050263828A1 High performance semiconductor devices fabricated with strain-induced processes and methods for making same 有权
公开(公告)号：US20050263828A1
公开(公告)日：2005-12-01
申请号：US11194084
申请日：2005-07-29
申请人： Chung-Hu Ke , Wen-Chin Lee , Yee-Chia Yeo , Chih-Hsin Ko , Chenming Hu
发明人： Chung-Hu Ke , Wen-Chin Lee , Yee-Chia Yeo , Chih-Hsin Ko , Chenming Hu
IPC分类号： H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/76 , H01L29/78 , H01L29/80
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L29/1033 , H01L29/78 , H01L29/7842
摘要： A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

54. 发明申请

US20050158923A1 Ultra-thin body transistor with recessed silicide contacts 审中-公开
标题翻译：具有凹陷硅化物触点的超薄体晶体管
公开(公告)号：US20050158923A1
公开(公告)日：2005-07-21
申请号：US11081104
申请日：2005-03-15
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L29/45 , H01L29/68 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/66636 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).
摘要翻译：一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210）（240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

55. 发明申请

US20050156274A1 Strained channel transistor and methods of manufacture 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US20050156274A1
公开(公告)日：2005-07-21
申请号：US11081919
申请日：2005-03-16
申请人： Yee-Chia Yeo , Chih-Hsin Ko , Wen-Chin Lee , Chenming Hu
发明人： Yee-Chia Yeo , Chih-Hsin Ko , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/00
CPC分类号： H01L29/7842 , H01L21/76229 , H01L21/76237 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.
摘要翻译：半导体器件包括其中形成有第一和第二隔离沟槽的半导体材料区域。第一隔离槽衬有具有低氧扩散速率的第一材料并填充绝缘材料。第二隔离槽不是衬有第一材料，而是用绝缘材料填充。形成在第一隔离区域附近的第一晶体管和邻近第二隔离区域形成的第二晶体管。

56. 发明申请

US20050147920A1 Method and system for immersion lithography 审中-公开
标题翻译：浸没式光刻法及系统
公开(公告)号：US20050147920A1
公开(公告)日：2005-07-07
申请号：US10748076
申请日：2003-12-30
申请人： Chia-Hui Lin , Yee-Chia Yeo
发明人： Chia-Hui Lin , Yee-Chia Yeo
IPC分类号： G03B27/00 , G03F7/00 , G03F7/11 , G03F7/20 , H01L21/00
CPC分类号： G03F7/70341 , G03F7/11
摘要： A system (100) and method for immersion lithography is disclosed in which an immersion medium (112) interfaces with a proximal lens (110) that focuses a patterned light beam on a light sensitive material (116), wherein the light sensitive material (116) is covered by a protective film (300) that interfaces with the immersion medium (112).
摘要翻译：公开了一种用于浸没式光刻的系统（100）和方法，其中浸没介质（112）与将图案化光束聚焦在光敏材料（116）上的近侧透镜（110）相接合，其中光敏材料）被与浸渍介质（112）接合的保护膜（300）覆盖。

57. 发明申请

US20050127400A1 Heterostructure resistor and method of forming the same 有权
标题翻译：异质结构电阻及其形成方法
公开(公告)号：US20050127400A1
公开(公告)日：2005-06-16
申请号：US10745831
申请日：2003-12-24
申请人： Yee-Chia Yeo , Wen-Chin Lee , Chih-Hsin Ko , Chung-Hu Ke , Chun-Chieh Lin , Chenming Hu
发明人： Yee-Chia Yeo , Wen-Chin Lee , Chih-Hsin Ko , Chung-Hu Ke , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L27/06 , H01L29/02 , H01L29/165 , H01L29/8605 , H01L31/109
CPC分类号： H01L27/0629 , H01L29/165 , H01L29/8605
摘要： A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.
摘要翻译：异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。掺杂区域包括覆盖半导体衬底的半导体层。半导体层包括具有第二自然晶格常数的第二半导体材料。

58. 发明申请

US20050056881A1 Dummy pattern for silicide gate electrode 审中-公开
标题翻译：硅化物栅电极的虚拟图案
公开(公告)号：US20050056881A1
公开(公告)日：2005-03-17
申请号：US10685938
申请日：2003-10-15
申请人： Yee-Chia Yeo , Chih-Hao Wang , Chenming Hu
发明人： Yee-Chia Yeo , Chih-Hao Wang , Chenming Hu
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/336 , H01L21/76 , H01L21/8234 , H01L27/092 , H01L29/78 , H01L29/788
CPC分类号： H01L21/28052 , H01L21/28097 , H01L21/31053
摘要： A semiconductor device having a plurality of silicided polysilicon structures in which the silicidation of the polysilicon structures is approximately uniform is provided. Dummy polysilicon structures are formed on the substrate prior to silicidation. The dummy polysilicon structures allow the surface of the wafer to be planarized without an excessive recess and causes the amount of metal available for the silicidation process to be approximately uniformly distributed among the various polysilicon structures.
摘要翻译：提供了具有多个硅化多晶硅结构的半导体器件，其中多晶硅结构的硅化物近似均匀。在硅化之前，在衬底上形成虚拟多晶硅结构。虚设多晶硅结构允许晶片的表面被平坦化而没有过多的凹陷，并且使可用于硅化工艺的金属的量大致均匀分布在各种多晶硅结构之间。

59. 发明授权

US06867433B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US06867433B2
公开(公告)日：2005-03-15
申请号：US10426566
申请日：2003-04-30
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

60. 发明申请

US20050045965A1 Device having multiple silicide types and a method for its fabrication 有权
标题翻译：具有多种硅化物类型的器件及其制造方法
公开(公告)号：US20050045965A1
公开(公告)日：2005-03-03
申请号：US10831021
申请日：2004-04-23
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/43 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

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