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51. 发明申请

US20060256635A1 Memory system with bit-line discharging mechanism 有权
标题翻译：具有位线放电机制的存储器系统
公开(公告)号：US20060256635A1
公开(公告)日：2006-11-16
申请号：US11128846
申请日：2005-05-13
申请人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C17/12 , G11C7/12 , G11C17/18
摘要： A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.
摘要翻译：公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线，在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。

52. 发明授权

US08958232B2 Method and apparatus for read assist to compensate for weak bit 有权
标题翻译：用于读取辅助补偿弱点的方法和装置
公开(公告)号：US08958232B2
公开(公告)日：2015-02-17
申请号：US13437081
申请日：2012-04-02
申请人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
发明人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C7/067 , G11C11/412 , G11C11/419
摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
摘要翻译：记忆辅助装置包括检测电路和补偿电路。检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

53. 发明授权

US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
标题翻译：用于在半导体器件中形成器件单元的布局方案和方法
公开(公告)号：US08928113B2
公开(公告)日：2015-01-06
申请号：US13082497
申请日：2011-04-08
申请人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
发明人： Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L27/108 , H01L29/94 , H01L21/70 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/1116 , H01L21/768 , H01L27/0207 , H01L27/11 , H01L2027/11887
摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
摘要翻译：用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

54. 发明授权

US08773930B2 Built-in test circuit and method 有权
标题翻译：内置测试电路及方法
公开(公告)号：US08773930B2
公开(公告)日：2014-07-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

55. 发明授权

US08675439B2 Bit line voltage bias for low power memory design 有权
标题翻译：用于低功耗存储器设计的位线电压偏置
公开(公告)号：US08675439B2
公开(公告)日：2014-03-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

56. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

57. 发明申请

US20130201776A1 BUILT-IN TEST CIRCUIT AND METHOD 有权
标题翻译：内置测试电路和方法
公开(公告)号：US20130201776A1
公开(公告)日：2013-08-08
申请号：US13365631
申请日：2012-02-03
申请人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
发明人： Tzu-Kuei LIN , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C29/006 , G11C29/06 , G11C2029/2602
摘要： A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
摘要翻译：测试半导体存储器的方法包括在封装半导体存储器之前执行第一类型的第一测试。第一类型的第一测试包括产生第一多个地址，解码第一多个地址以在第一解码器处产生第二多个解码地址，以及激活半导体的多个行或多个列中的一个基于第二多个解码地址的存储器。在执行第一类型的第一测试之后封装半导体存储器。

58. 发明授权

US08482990B2 Memory edge cell 有权
标题翻译：内存边缘单元格
公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

59. 发明授权

US08406075B2 Ultra-low leakage memory architecture 有权
标题翻译：超低泄漏存储器架构
公开(公告)号：US08406075B2
公开(公告)日：2013-03-26
申请号：US12694032
申请日：2010-01-26
申请人： Cheng Hung Lee , Hung-Jen Liao
发明人： Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/063
摘要： An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.
摘要翻译：集成电路结构包括有源电源线和数据保持电源线。存储器宏连接到有源电源线和数据保持电源线。存储器宏包括存储单元阵列和开关。该开关被配置为在将存储单元阵列连接到有源电源线之间切换连接，并将存储单元阵列连接到数据保持电源线。数据保持电源线在存储器宏之外。

60. 发明申请

US20120313177A1 Multiple Finger Structure 有权
标题翻译：多指结构
公开(公告)号：US20120313177A1
公开(公告)日：2012-12-13
申请号：US13158133
申请日：2011-06-10
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/088 , H01L27/1104
摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.
摘要翻译：多指结构包括放置在一对虚拟POLY线之间的多个有源区域。有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。有源区域与虚拟POLY线路延伸并重叠。有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

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