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51. 发明授权

US07994885B2 High-frequency switch in multi-layer substrate 有权
标题翻译：高频开关在多层基板上
公开(公告)号：US07994885B2
公开(公告)日：2011-08-09
申请号：US12860739
申请日：2010-08-20
申请人： Chang-Lin Wei , Ching-Liang Weng , Uei-Ming Jow , Ying-Jiunn Lai , Syun Yu , Chang-Sheng Chen
发明人： Chang-Lin Wei , Ching-Liang Weng , Uei-Ming Jow , Ying-Jiunn Lai , Syun Yu , Chang-Sheng Chen
IPC分类号： H01H51/22
CPC分类号： H05K1/162 , H01P1/15 , H05K1/0237 , H05K1/113 , H05K1/165 , H05K1/167 , H05K3/4644 , H05K2201/09672
摘要： A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.
摘要翻译：交换机模块由建立的多层结构和一些无源设备组成。积层多层结构具有彼此层叠的多个导电层和电介质层。至少一个电介质层在任何两个导电层之间被干扰。任何一个无源器件是至少一个导电层的一部分，并且电连接多层结构的表面上的多个导电焊盘。

52. 发明授权

US07936243B2 Adjustable resistor embedded in multi-layered substrate and method for forming the same 失效
标题翻译：嵌入多层基板的可调电阻及其形成方法
公开(公告)号：US07936243B2
公开(公告)日：2011-05-03
申请号：US11488608
申请日：2006-07-19
申请人： Ying-Jiunn Lai , Chang-Sheng Chen , Chin-Sun Shyu , Uei-Ming Jow , Chang-Lin Wei
发明人： Ying-Jiunn Lai , Chang-Sheng Chen , Chin-Sun Shyu , Uei-Ming Jow , Chang-Lin Wei
IPC分类号： H01F27/28
CPC分类号： H01C17/23 , H01C7/003 , H05K1/167 , H05K3/0047 , H05K2203/171 , H05K2203/175
摘要： An adjustable resistor embedded in a multi-layered substrate and method for forming the same. The adjustable resistor comprises: a planar resistor, having a plurality of terminals; and a plurality of connecting lines connected to the planar resistor, each of the connecting lines being drawn from each of the terminals of the planar resistor so as to form a resistor network, wherein the connecting lines are selectively broken by a process for drilling the substrate to form a number of combinations of opened connecting lines such that the resistance value of the adjustable resistor is varied and thus the resistance value of the adjustable resistor can be precisely adjusted.
摘要翻译：嵌入多层基板中的可调电阻及其形成方法。可调电阻器包括：具有多个端子的平面电阻器; 以及连接到平面电阻器的多个连接线，每个连接线从平面电阻器的每个端子拉出以形成电阻器网络，其中通过用于钻取基板的工艺来选择性地断开连接线以形成打开的连接线的多个组合，使得可调节电阻器的电阻值变化，从而可以精确地调节可调电阻器的电阻值。

53. 发明授权

US07528433B2 Capacitor structure 有权
标题翻译：电容结构
公开(公告)号：US07528433B2
公开(公告)日：2009-05-05
申请号：US11456094
申请日：2006-07-07
申请人： Uei-Ming Jow , Chang-Sheng Chen , Ying-Jiunn Lai , Chin-Sun Shyu
发明人： Uei-Ming Jow , Chang-Sheng Chen , Ying-Jiunn Lai , Chin-Sun Shyu
IPC分类号： H01L29/00
CPC分类号： H05K1/162 , H01G4/232 , H01G4/306 , H01L23/50 , H01L23/5223 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H05K1/0298 , H05K2201/09236 , H05K2201/09672 , H01L2924/00
摘要： A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.
摘要翻译：提供了具有交叉耦合设计的电容器结构。在电容器结构中，通过在另一电极上方或下方或旁边交叉耦合电极将导线或电极板耦合在一起。通过交叉耦合和较少的通孔，可以在最小区域内获得最大的电容值。所提供的电容器结构也可以应用于高频高速模块或系统，以增强电容性基板的噪声抑制能力。

54. 发明授权

US07515435B2 Multi-functional composite substrate structure 失效
标题翻译：多功能复合基板结构
公开(公告)号：US07515435B2
公开(公告)日：2009-04-07
申请号：US11646339
申请日：2006-12-28
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译：提供了多功能复合基板结构。具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。可以在第一基板上制造一个或多个电容器。此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。因此，有效地提高了电感器的电感。此外，内置组件的面积减少。此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

55. 发明授权

US07471166B2 Balanced-to-unbalanced transformer embedded with filter 失效
标题翻译：平衡 - 不平衡变压器嵌入式滤波器
公开(公告)号：US07471166B2
公开(公告)日：2008-12-30
申请号：US11633545
申请日：2006-12-05
申请人： Chang-Lin Wei , Chang-Sheng Chen , Syun Yu , Ying-Jiunn Lai , Uei-Ming Jow
发明人： Chang-Lin Wei , Chang-Sheng Chen , Syun Yu , Ying-Jiunn Lai , Uei-Ming Jow
IPC分类号： H01P5/10 , H01P1/20 , H01P1/203
CPC分类号： H01P5/10
摘要： A balanced-to-unbalanced transformer embedded with a filter, the balanced-to-unbalanced transformer being disposed in a multi-layered substrate and comprising vertically coupled transmission lines designed in different layers in the multi-layer substrate to increase transmission performances. A capacitor and a transmission line are connected to a single-ended I/O port of the balanced-to-unbalanced transformer such that a filter is embedded in the balanced-to-unbalanced transformer.
摘要翻译：一种嵌入滤波器的平衡不平衡变压器，平衡不平衡变压器设置在多层衬底中，并且包括在多层衬底中以不同层设计的垂直耦合传输线，以增加传输性能。电容器和传输线连接到平衡不平衡变压器的单端I / O端口，使得滤波器嵌入在平衡不平衡变压器中。

56. 发明申请

US20070168148A1 Test method of embedded capacitor and test system thereof 失效
标题翻译：嵌入式电容器的测试方法及其测试系统
公开(公告)号：US20070168148A1
公开(公告)日：2007-07-19
申请号：US11591381
申请日：2006-11-01
申请人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
发明人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G01R31/2818 , G01R31/2805 , G01R31/304
摘要： A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.
摘要翻译：提供了一种嵌入式电容器及其测试系统的测试方法。该方法和系统用于确定电路板基板中的嵌入式电容元件的电气规格，从而避免执行不满足期望规格的电路板基板的后续制造工艺。在该方法和系统中，测量嵌入式电容器的几何尺寸，并从模型数据库中获得电参数和几何尺寸之间的关系值以及标准电参数，以计算嵌入式电容器的电参数。然后，将嵌入式电容器的电气参数与标准电气参数进行比较，以获得误差值。因此，根据误差值，可以获取电路板基板是否满足设定的电气规格。

57. 发明申请

US20070133182A1 Multi-layered printed circuit board embedded with filter 失效
标题翻译：多层印刷电路板嵌入式滤波器
公开(公告)号：US20070133182A1
公开(公告)日：2007-06-14
申请号：US11438363
申请日：2006-05-23
申请人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
发明人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
IPC分类号： H05K7/00
CPC分类号： H05K1/162 , H03H7/09 , H03H7/1775 , H03H2001/0085 , H05K3/4626 , H05K3/4688 , H05K2201/09236 , H05K2201/09672
摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.
摘要翻译：嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。至少一个电容器是设置在低电介质材料上的叉指电容器。叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性。也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。

58. 发明申请

US20060261482A1 Apparatus and method for testing component built in circuit board 有权
标题翻译：用于测试电路板内置组件的装置和方法
公开(公告)号：US20060261482A1
公开(公告)日：2006-11-23
申请号：US11131741
申请日：2005-05-18
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen
IPC分类号： H01L23/52
CPC分类号： H05K1/0268 , G01R31/2818 , H05K1/0298 , H05K1/116 , H05K1/162 , H05K1/165 , H05K1/167
摘要： A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.
摘要翻译：一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径通过所述一个端子到所述至少一个测试垫中的每一个。

59. 发明申请

US20060176123A1 High-frequency switch in multi-layer substrate 审中-公开
标题翻译：高频开关在多层基板上
公开(公告)号：US20060176123A1
公开(公告)日：2006-08-10
申请号：US11157068
申请日：2005-06-20
申请人： Chang-Lin Wei , Ching-Liang Weng , Uei-Ming Jow , Ying-Jiunn Lai , Syun Yu , Chang-Sheng Chen
发明人： Chang-Lin Wei , Ching-Liang Weng , Uei-Ming Jow , Ying-Jiunn Lai , Syun Yu , Chang-Sheng Chen
IPC分类号： H01P1/10
CPC分类号： H05K1/162 , H01P1/15 , H05K1/0237 , H05K1/113 , H05K1/165 , H05K1/167 , H05K3/4644 , H05K2201/09672
摘要： A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.
摘要翻译：交换机模块由建立的多层结构和一些无源设备组成。积层多层结构具有彼此层叠的多个导电层和电介质层。至少一个电介质层在任何两个导电层之间被干扰。任何一个无源器件是至少一个导电层的一部分，并且电连接多层结构的表面上的多个导电焊盘。

60. 发明申请

US20060108671A1 Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys 有权
标题翻译：半导体封装包括插入在杯形引线框架和具有台面和谷底的引线框架之间的管芯
公开(公告)号：US20060108671A1
公开(公告)日：2006-05-25
申请号：US10996148
申请日：2004-11-23
申请人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
发明人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3107 , H01L23/49513 , H01L23/49562 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/84 , H01L2224/16245 , H01L2224/32245 , H01L2224/37147 , H01L2224/40245 , H01L2224/73253 , H01L2224/83801 , H01L2224/84385 , H01L2224/84801 , H01L2924/01004 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
摘要翻译：半导体封装包括在上引线框架和下引线框架之间插入倒装芯片的管芯。下引线框架具有与芯片底表面上的端子对准的触点。上引线框架接触管芯顶部的端子，并且上引线框架的边缘围绕模具的边缘向下弯曲，使上引线框架成杯形。上引线框架的边缘接触下引线框架的另一部分，使得封装的所有触点是共面的，并且可以表面安装在印刷电路板上。芯片的端子通过焊料层电连接到引线框架。预定了将管芯与引线框架连接的各个焊料层的厚度，以通过许多热循环来优化封装的性能。这是通过用多个台面制造下引线框架并使用双重回流焊工艺来完成的。

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