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51. 发明授权

US07839650B2 Circuit board structure having embedded capacitor and fabrication method thereof 失效
标题翻译：具有嵌入式电容器的电路板结构及其制造方法
公开(公告)号：US07839650B2
公开(公告)日：2010-11-23
申请号：US11977780
申请日：2007-10-25
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H05K1/18
CPC分类号： H05K1/162 , H05K3/107 , H05K3/108 , H05K3/426 , H05K3/4602 , H05K3/4688 , H05K2201/0376 , H05K2201/09036 , H05K2201/09536 , H05K2201/09672 , Y10T29/49146
摘要： The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability.
摘要翻译：本发明提供一种具有嵌入式电容器的电路板结构及其制造方法。电路板结构包括具有至少一个具有非穿透性第一和第二槽的表面的芯层板，分别形成在芯层板的第一和第二槽中的电路层和第一电极板，并且与芯体齐平层板; 形成在所述芯层基板，所述电路层和所述第一电极板上的高介电材料层; 形成在高电介质材料层上并对应于第一电极板的第二电极板，从而通过第一和第二电极板和高电介质材料层形成电容器。高介电材料层形成在平面上，以消除填充不良，提高可靠性。

52. 发明授权

US07812460B2 Packaging substrate and method for fabricating the same 有权
标题翻译：包装基板及其制造方法
公开(公告)号：US07812460B2
公开(公告)日：2010-10-12
申请号：US12474654
申请日：2009-05-29
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K3/243 , H01L23/49816 , H01L23/49866 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/01046 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/181 , H05K1/111 , H05K3/3436 , H05K2201/0367 , H05K2201/0391 , H05K2203/049 , H05K2203/054 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
摘要： A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications.
摘要翻译：提出了一种封装基板及其制造方法，包括：提供具有第一表面和相对的第二表面的基板主体，其中第一表面具有多个倒装芯片焊盘和引线接合焊盘，第二表面具有多个焊球垫; 在第一和第二表面上形成第一和第二焊料掩模层，并在第一和第二焊料掩模层中形成开口以暴露倒装芯片焊盘，引线接合焊盘和焊球焊盘; 在倒装焊盘上形成第一凸点; 以及通过化学镀在所述第一凸块和所述引线接合焊盘上形成化学镀Ni / Pd / Au层，其中所述无电镀Ni / Pd / Au层具有能够满足细间距应用的均匀性要求的厚度公差。

53. 发明申请

US20100052148A1 PACKAGE STRUCTURE AND PACKAGE SUBSTRATE 审中-公开
标题翻译：包装结构和包装衬底
公开(公告)号：US20100052148A1
公开(公告)日：2010-03-04
申请号：US12541253
申请日：2009-08-14
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/498
CPC分类号： H05K1/112 , H01L21/563 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05111 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05611 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/73203 , H01L2224/81193 , H01L2224/81801 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H05K3/3436 , H05K2201/094 , H05K2201/09436 , H05K2201/09472 , H05K2201/09509 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/00014
摘要： Provided are a package structure and a package substrate, including: a substrate body having a plurality of matrix-arranged electrical contact pads formed on at least one surface thereof, wherein a solder mask layer is formed on said surface and has a plurality of openings for exposing the electrical contact pads, respectively; a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at the peripheries of the openings; and a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure. By forming the even electroless-plated layers on the electrical contact pads. The invention overcomes drawbacks of the prior art, namely breakage of interfaces between solder bumps and electrical contact pads and even damage of the package structure otherwise caused by excessive differences in stress between the solder bumps.
摘要翻译：提供一种封装结构和封装基板，包括：基板主体，其具有形成在其至少一个表面上的多个矩阵布置的电接触焊盘，其中在所述表面上形成焊接掩模层，并且具有多个开口，分别暴露电接触垫; 设置在电接触垫上，开口壁上和开口周边的第一化学镀层; 以及设置在所述第一化学镀层上的第二无电镀层，所述第一和第二无电镀层构成凹陷的电连接结构。通过在电接触焊盘上形成均匀的无电镀层。本发明克服了现有技术的缺点，即焊料凸块与电接触焊盘之间的界面的破坏，甚至损坏包装结构，否则由焊料凸块之间的应力过大的差异引起。

54. 发明申请

US20100029047A1 METHOD OF FABRICATING PRINTED CIRCUIT BOARD HAVING SEMICONDUCTOR COMPONENTS EMBEDDED THEREIN 审中-公开
标题翻译：制作嵌入式半导体元件的印刷电路板的制作方法
公开(公告)号：US20100029047A1
公开(公告)日：2010-02-04
申请号：US12510379
申请日：2009-07-28
申请人： Shih-Ping Hsu , Wei Che Lin
发明人： Shih-Ping Hsu , Wei Che Lin
IPC分类号： H01L21/52
CPC分类号： H05K1/185 , H01L23/13 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2221/68345 , H01L2224/04105 , H01L2224/24227 , H01L2924/01006 , H01L2924/01033 , H01L2924/14 , H01L2924/15156 , H01L2924/18162 , H05K3/4602 , H05K2201/10674
摘要： A method for fabricating a printed circuit board having semiconductor components embedded therein is provided. A carrier board having at least a predetermined hole area is provided. A plurality of through holes are formed in the surround of the predetermined hole area on the carrier board. A rectangular cavity is formed by punching to remove the predetermined hole area, and a plurality of through holes are formed around the rectangular cavity The through holes facilitate receipt of the semiconductor chip and filling of a fixing material in the rectangular cavity, to avoid displacement of the semiconductor chip in subsequent fabricating steps that would otherwise cause a drawback, that is, a wiring to be formed later is improperly electrically connected to the semiconductor chip.
摘要翻译：提供了一种制造其中嵌有半导体元件的印刷电路板的方法。提供具有至少预定孔面积的载板。在承载板上的预定孔区域的周围形成有多个通孔。通过冲压形成矩形空腔以去除预定的孔区域，并且在矩形空腔周围形成多个通孔。通孔便于半导体芯片的接收和矩形空腔中的固定材料的填充，以避免位移否则将导致缺点的后续制造步骤中的半导体芯片，即稍后形成的布线不正确地电连接到半导体芯片。

55. 发明授权

US07629204B2 Surface roughening method for embedded semiconductor chip structure 有权
标题翻译：嵌入式半导体芯片结构的表面粗糙化方法
公开(公告)号：US07629204B2
公开(公告)日：2009-12-08
申请号：US11432369
申请日：2006-05-12
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L21/00
CPC分类号： H01L24/19 , H01L23/3142 , H01L23/5387 , H01L23/5389 , H01L24/24 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/18162 , H05K1/185 , H05K3/381 , Y10S438/964
摘要： A surface roughening method for an embedded semiconductor chip structure is proposed. The method includes providing a carrier board with an opening and mounting a semiconductor chip in the opening of the carrier board, the semiconductor chip having a plurality of electrode pads; and performing a surface roughening process on a surface of the electrode pads of the semiconductor chip, so as to form a rough structure on a surface of the semiconductor chip exposed by the opening of the carrier board. Thus, adhesion between the chip and a dielectric layer is improved during subsequently forming circuit build-up layers on the roughened surface of the semiconductor chip and on the surface of carrier board.
摘要翻译：提出了一种嵌入式半导体芯片结构的表面粗糙化方法。该方法包括：在载板的开口中提供具有开口并将半导体芯片安装的载体板，所述半导体芯片具有多个电极焊盘; 以及在半导体芯片的电极焊盘的表面上进行表面粗糙化处理，以便在由载体板的开口暴露的半导体芯片的表面上形成粗糙结构。因此，随后在半导体芯片的粗糙化表面上和载体板的表面上形成电路堆积层期间，芯片和电介质层之间的粘合性得到改善。

56. 发明授权

US07582961B2 Package structure with circuits directly connected to semiconductor chip 有权
标题翻译：封装结构，电路直接连接到半导体芯片
公开(公告)号：US07582961B2
公开(公告)日：2009-09-01
申请号：US12020693
申请日：2008-01-28
申请人： Kan-Jung Chia , Shih-Ping Hsu
发明人： Kan-Jung Chia , Shih-Ping Hsu
IPC分类号： H01L23/12 , H01L23/053
CPC分类号： H01L23/3128 , H01L23/13 , H01L23/3142 , H01L23/49816 , H01L23/49833 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/83 , H01L2224/04105 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/12105 , H01L2224/13147 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/8385 , H01L2924/0001 , H01L2924/00014 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/18162 , H01L2924/00 , H01L2224/29099 , H01L2224/05599 , H01L2224/05099
摘要： A package structure with circuit directly connected to semiconductor chip, which comprises: a carrier board, a semiconductor chip, and at least a built-up structure. The carrier board is formed with a through cavity therein. The semiconductor chip is mounted in the through cavity of the carrier board, and a lateral surface of the semiconductor chip is coated by an adhesive material which is not contacted by the carrier board. The built-up structure, which includes a dielectric layer, is disposed on the surface of the carrier board and an active surface of the semiconductor chip. Part surface of the dielectric layer is exposed by the through cavity. The present invention decreases warpage of the packaging structure resulting from asymmetrical built-up structures.
摘要翻译：具有直接连接到半导体芯片的电路的封装结构，其包括：载板，半导体芯片和至少一个建立结构。载板在其中形成有通孔。半导体芯片安装在承载板的通孔中，并且半导体芯片的侧表面由不与载板接触的粘合材料涂覆。包括电介质层的积层结构设置在载体板的表面和半导体芯片的有效表面上。电介质层的部分表面被通孔暴露。本发明减少了由不对称组合结构引起的包装结构翘曲。

57. 发明申请

US20090102045A1 Packaging substrate having capacitor embedded therein 审中-公开
标题翻译：其中包含电容器的封装基板
公开(公告)号：US20090102045A1
公开(公告)日：2009-04-23
申请号：US12285957
申请日：2008-10-17
申请人： Shih-Ping Hsu , Wen-Sung Chang , Chih-Kui Yang
发明人： Shih-Ping Hsu , Wen-Sung Chang , Chih-Kui Yang
IPC分类号： H01L23/12
CPC分类号： H01L23/50 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A packaging substrate having capacitors embedded therein, comprising: two capacitor disposition layers, each respectively consisting of a high dielectric layer and two first circuit layers disposed on two opposite surfaces of the high dielectric layer, wherein each of the first circuit layers has a plurality of electrode plates and a plurality of circuits; an adhesive layer disposed between the capacitor disposition layers to adhere the capacitor disposition layers to form a core board structure, wherein spaces between the circuits of every first circuit layer are filled with the adhesive layer; and a plurality of conductive through holes penetrating the capacitor disposition layers and the adhesive layer, and electrically connecting the circuits of the capacitor disposition layers respectively; wherein, pairs of the electrode plates on the opposite surfaces of each of the capacitor disposition layers are parallel and correspond to each other to form capacitors.
摘要翻译：一种具有嵌入其中的电容器的封装衬底，包括：两个电容器配置层，每个电容器配置层分别由高电介质层和设置在高电介质层的两个相对表面上的两个第一电路层组成，其中每个第一电路层具有多个电极板和多个电路; 设置在电容器配置层之间的粘合剂层，以粘附电容器配置层以形成芯板结构，其中每个第一电路层的电路之间的空间用粘合剂层填充; 以及穿过电容器配置层和粘合剂层的多个导电通孔，并分别电连接电容器配置层的电路; 其中，每个电容器配置层的相对表面上的电极板对成对平行并彼此对应以形成电容器。

58. 发明申请

US20090041981A1 PACKAGING SUBSTRATE HAVING ELECTRICAL CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有电连接结构的包装基板及其制造方法
公开(公告)号：US20090041981A1
公开(公告)日：2009-02-12
申请号：US12188663
申请日：2008-08-08
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： B32B3/24 , H05K3/00
CPC分类号： H05K3/3473 , H01L21/4853 , H01L23/49816 , H01L2224/0401 , H01L2224/05563 , H01L2224/05571 , H01L2224/13006 , H01L2224/13022 , H01L2224/13109 , H01L2924/0002 , H01L2924/01327 , H05K3/244 , H05K3/3452 , H05K3/4007 , H05K2201/0367 , H05K2201/0989 , H05K2203/043 , H05K2203/054 , Y10T428/24331 , H01L2924/00 , H01L2224/05552
摘要： A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability.
摘要翻译：提供具有电连接结构的封装基板及其制造方法。封装基板具有在其表面上具有多个导电焊盘的基板主体; 焊接掩模层，其设置在所述基板主体上，具有对应于所述导电焊盘的多个开口，每个所述开口的尺寸大于每个所述导电焊盘; 以及用于覆盖导电焊盘的电镀焊料凸块，以提供更好的粘合强度和可靠性。

59. 发明申请

US20090032930A1 PACKAGING SUBSTRATE HAVING CHIP EMBEDDED THEREIN AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有嵌入芯片的包装基板及其制造方法
公开(公告)号：US20090032930A1
公开(公告)日：2009-02-05
申请号：US11832466
申请日：2007-08-01
申请人： Shih-Ping Hsu , Chung-Cheng Lien , Shang-Wei Chen , Kan-Jung Chia
发明人： Shih-Ping Hsu , Chung-Cheng Lien , Shang-Wei Chen , Kan-Jung Chia
IPC分类号： H01L21/52 , H01L23/18
CPC分类号： H01L21/52 , H01L23/24 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2924/14 , H01L2924/18162 , H01L2924/00
摘要： A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed.
摘要翻译：具有嵌入其中的芯片的封装基板包括其中具有第一腔的第一铝基板; 第二铝基板，具有对应于第一空腔的第二腔; 设置在所述第一铝基板和所述第二铝基板之间的电介质层; 嵌入在所述第一腔和所述第二腔中的芯片，具有其上具有多个电极焊盘的活性表面; 以及设置在第一铝基板的表面和芯片的有源表面上的一个堆积结构，其中，所述积层结构具有电连接到电极焊盘的多个导电通孔。通过使用铝或铝合金作为基材的材料，显着减少了基板翘曲。另外，公开了一种制造具有嵌入其中的芯片的封装衬底的方法。

60. 发明申请

US20090032294A1 CIRCUIT BOARD 有权
标题翻译：电路板
公开(公告)号：US20090032294A1
公开(公告)日：2009-02-05
申请号：US12122014
申请日：2008-05-16
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H05K1/09
CPC分类号： H05K3/3473 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05567 , H01L2224/05644 , H01L2224/05671 , H01L2224/13109 , H05K3/243 , H05K3/3452 , H05K2201/0367 , H05K2201/0989 , H05K2203/043 , H05K2203/0542 , H01L2924/00014
摘要： Provided is a circuit board including: a circuit board body with at least one surface having a plurality of electrically connecting pads; an insulating protection layer formed on the circuit board body and formed with an opening corresponding in position to one of the electrically connecting pads, being larger than the electrically connecting pad, and not being in contact with the periphery of the electrically connecting pad; and a soldering material formed on, and confined to, the electrically connecting pad; thus allowing an electrically conductive element limited in the opening formed in the insulating protection layer to be fabricated from the soldering material by a reflow process with a view to forming a fine-pitch electrically connecting structure.
摘要翻译：提供一种电路板，包括：具有至少一个具有多个电连接焊盘的表面的电路板主体; 绝缘保护层，形成在所述电路板主体上，并且形成有与所述电连接焊盘中的一个对应的开口，大于所述电连接焊盘，并且不与所述电连接焊盘的周边接触; 以及形成在所述电连接焊盘上并限制于所述电连接焊盘的焊接材料; 从而允许在绝缘保护层中形成的开口中限制的导电元件通过回流工艺由焊接材料制成，以形成细间距电连接结构。

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