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51. 发明授权

US06438022B2 Memory cell configuration 失效
标题翻译：内存单元配置
公开(公告)号：US06438022B2
公开(公告)日：2002-08-20
申请号：US09854259
申请日：2001-05-10
申请人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
发明人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
摘要翻译：存储单元结构的存储单元分别具有选择晶体管，存储晶体管和铁电电容器。选择晶体管和存储晶体管串联连接。铁电电容器连接在存储晶体管的控制电极和选择晶体管的第一端子之间。

52. 发明授权

US06399433B2 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US06399433B2
公开(公告)日：2002-06-04
申请号：US09773218
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/55
摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
摘要翻译：一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。在该间隙中形成单元板电极，并在该层中形成沟槽。沟槽达到第一插头表面的最远处，并且填充有绝缘层。该层被删除。形成具有高ε或铁电介质的存储电容器和存储节点电极。电容器设置在身体内和上方的第二平面内。绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

53. 发明授权

US06265748B1 Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement 失效
标题翻译：垂直MOS晶体管根据存储的数据具有至少三个不同阈值电压的存储单元布置，以及制造所述布置的方法
公开(公告)号：US06265748B1
公开(公告)日：2001-07-24
申请号：US09180129
申请日：1998-11-02
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： H01L2976
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译：一种存储单元布置及其制造方法，其包括作为存储单元的垂直MOS晶体管，其中通过多级编程通过晶体管的至少三个不同的阈值电压值来存储信息。通过厚氧化物晶体管的栅极电介质的厚度获得一个阈值电压值，并且通过不同的沟道掺杂获得其它阈值电压值。可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

54. 发明授权

US06242319B1 Method for fabricating an integrated circuit configuration 失效
标题翻译：制造集成电路结构的方法
公开(公告)号：US06242319B1
公开(公告)日：2001-06-05
申请号：US09498530
申请日：2000-02-04
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L2176
CPC分类号： H01L27/10858 , H01L23/544 , H01L25/50 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A first structure of a circuit configuration and a first alignment structure are produced in the region of a surface of a first substrate. The first alignment structure scatters electron beams differently than its surroundings. A second substrate, which is more transmissive to electron beams than the first alignment structure, is connected to the first substrate in such a way that the second substrate is disposed above the surface of the first substrate. In order to align a mask with respect to the first structure, a position of the first alignment structure is determined with the aid of electron beams. With the aid of the mask, at least one second structure of the circuit configuration is produced in the region of an uncovered upper surface of the second substrate. The first structure may be a metallic line encapsulated by insulating material. A contact may connect the first structure to the second structure. With the aid of electron beam lithography, at least one second alignment structure may be produced in the region of the upper surface of the second substrate, using which the mask is aligned.
摘要翻译：在第一基板的表面的区域中制造电路结构和第一对准结构的第一结构。第一对准结构与其周围环境不同地散射电子束。与第一对准结构相比，对电子束更透射的第二衬底以这样的方式连接到第一衬底，使得第二衬底设置在第一衬底的表面之上。为了使掩模相对于第一结构对准，借助于电子束来确定第一对准结构的位置。借助于掩模，在第二基板的未覆盖的上表面的区域中产生电路构造的至少一个第二结构。第一结构可以是由绝缘材料包封的金属线。触点可以将第一结构连接到第二结构。借助于电子束光刻技术，可以在第二衬底的上表面的区域中产生至少一个第二对准结构，使用掩模进行对准。

55. 发明授权

US06229169B1 Memory cell configuration, method for fabricating it and methods for operating it 失效
标题翻译：存储单元配置，其制造方法及其操作方法
公开(公告)号：US06229169B1
公开(公告)日：2001-05-08
申请号：US09213724
申请日：1998-12-17
申请人： Franz Hofmann , Wolfgang Krautschneider , Wolfgang Rösner , Lothar Risch , Till Schlösser , Paul-Werner Basse
发明人： Franz Hofmann , Wolfgang Krautschneider , Wolfgang Rösner , Lothar Risch , Till Schlösser , Paul-Werner Basse
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11507
摘要： A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.
摘要翻译：存储单元配置在半导体衬底中包含多个存储单元。每个存储单元具有连接在位线和存储元件之间的选择晶体管。每个存储器单元可以通过第一字线和第二字线驱动，第一字线和第二字线彼此交叉。存储单元配置尤其是DRAM配置。

56. 发明授权

US6064101A Read-only memory cell arrangement 失效
标题翻译：只读存储单元布置
公开(公告)号：US6064101A
公开(公告)日：2000-05-16
申请号：US77268
申请日：1998-06-08
申请人： Wolfgang Krautschneider , Frank Lau , Franz Hofmann
发明人： Wolfgang Krautschneider , Frank Lau , Franz Hofmann
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1128 , H01L27/112
摘要： A read-only memory cell arrangement having planar MOS transistors which are arranged in parallel rows. Neighboring rows run alternately on the bottom of longitudinal trenches and run between neighboring longitudinal trenches. Bit lines run transversely and word lines run parallel to the longitudinal trenches. The memory cell arrangement can be produced with an area per memory cell of 2F.sup.2 (F-minimum structure size).
摘要翻译： PCT No.PCT / DE96 / 02328 Sec。 371日期1998年6月8日第 102（e）1998年6月8日PCT PCT 1996年12月5日PCT公布。公开号WO97 / 22139 日期：1996年6月19日具有并列排列的平面MOS晶体管的只读存储单元布置。相邻的行交替地在纵向沟槽的底部延伸并且在相邻的纵向沟槽之间延伸。位线横向延伸，字线平行于纵向沟槽延伸。存储单元布置可以产生具有2F2（F-最小结构尺寸）的每个存储单元的面积。

57. 发明授权

US5920778A Read-only memory cell arrangement and method for its production 失效
标题翻译：只读存储单元布置及其生产方法
公开(公告)号：US5920778A
公开(公告)日：1999-07-06
申请号：US913740
申请日：1997-09-23
申请人： Wolfgang Rosner , Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
发明人： Wolfgang Rosner , Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/11273 , H01L27/112
摘要： In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). The width of the insulation trenches (16) is preferably equal to their separation, so that the memory cell arrangement can be produced with a space requirement of 2F.sup.2 per memory cell, F being the minimum structure size in the respective technology.
摘要翻译： PCT No.PCT / DE96 / 00614 Sec。 371日期1997年9月23日 102（e）1997年9月23日PCT PCT 1996年4月9日PCT公布。公开号WO96 / 3351300 日期1996年10月24日在具有包含垂直MOS晶体管的第一存储单元且具有不包含垂直MOS晶体管的第二存储单元的只读存储单元布置中，存储单元沿着带状平行的相对侧布置绝缘沟槽（16）。绝缘沟槽（16）的宽度优选等于它们的间隔，使得可以以每个存储单元的空间要求为2F2来生产存储单元布置，F是相应技术中的最小结构尺寸。

58. 发明授权

US5559353A Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof 失效
标题翻译：具有至少一个CMOS-NAND门的集成电路结构及其制造方法
公开(公告)号：US5559353A
公开(公告)日：1996-09-24
申请号：US332737
申请日：1994-11-01
申请人： Lothar Risch , Thomas Vogelsang , Franz Hofmann , Karl Hofmann
发明人： Lothar Risch , Thomas Vogelsang , Franz Hofmann , Karl Hofmann
IPC分类号： H01L21/8238 , H01L21/762 , H01L27/092 , H03K19/0948 , H01L29/78
CPC分类号： H03K19/0948 , H01L21/76294 , H01L27/0922
摘要： A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.
摘要翻译：第一MOS晶体管和第二MOS晶体管与彼此并联连接的第一互补MOS晶体管和第二互补MOS晶体管串联连接。晶体管各自被实现为形成源极，沟道和漏极的垂直层序列，并且其具有设置栅极电介质和栅电极的侧壁。在源极，沟道和漏极的公共层序列中实现彼此并联连接的互补MOS晶体管。形成串联晶体管的层序列彼此重叠。电路结构通过层序列的上层定义（例如通过分子束外延）来制造。

59. 发明授权

US4964668A Top for vehicles, particularly passenger cars 失效
标题翻译：特别是乘用车
公开(公告)号：US4964668A
公开(公告)日：1990-10-23
申请号：US400718
申请日：1989-08-30
申请人： Franz Hofmann
发明人： Franz Hofmann
IPC分类号： B60J7/12
CPC分类号： B60J7/1226
摘要： For a top of a passenger car, a noise/thermal insulating intermediate layer and an interior ceiling are arranged inside an exterior top covering of the top for muffling noise and for achieving an effective thermal protection against heat and coldness. So that an inflating of the top covering is avoided during a driving operation at speed, the top covering, supporting layers of the intermediate layer and the interior ceiling are attached to a plurality of transversely extending bows of the top.
摘要翻译：对于乘用车的顶部，噪音/隔热中间层和内部天花板布置在顶部的外部顶部覆盖物内，用于消声噪声并且实现有效的热保护以防止热和冷。因此，在速度的驾驶操作期间避免了顶盖的膨胀，中间层的顶盖，支撑层和内部天花板附接到顶部的多个横向延伸的弓。

60. 发明授权

US4713180A Ceramic filter and method for using same 失效
标题翻译：陶瓷过滤器及其使用方法
公开(公告)号：US4713180A
公开(公告)日：1987-12-15
申请号：US701135
申请日：1985-02-13
申请人： Franz Hofmann , Hans G. Trapp , Rolf Rietzscher , Jurgen Otto , Wolfgang Kaettlitz , Gerd Trinki
发明人： Franz Hofmann , Hans G. Trapp , Rolf Rietzscher , Jurgen Otto , Wolfgang Kaettlitz , Gerd Trinki
IPC分类号： B01D39/20 , B22D1/00 , B22D43/00 , C04B38/00 , C21C1/00 , C21C7/00 , C22B4/00 , C22B9/02 , B01D29/32
CPC分类号： C21C1/00 , B01D39/2093 , C04B38/00 , C21C7/00 , C22B9/023 , Y02P10/234
摘要： A ceramic filter for filtering molten iron is disclosed. The ceramic filter is made from a high-melting ceramic material having an open-celled foam structure, a variable bulk density in different portions of the filter, and at least one afflux surface. In order to filter molten iron efficiently, the ratio of filter surface to filter volume should be in the range of about 0.0003 to 9 m.sup.2 /cm.sup.3, the specific filter resistance should be in the range of about 0.1 to 0.9 bar-cm at a flow rate of 5 m.sup.3 /hour, and the pressure loss .DELTA.p across the filter should depend on the specific resistance .rho., the filter length, and the surface area of the afflux plane F in accordance with the relationship: ##EQU1## A method for filtering molten iron using this ceramic filter is also disclosed. In this method, the ceramic filter is located near the point in the casting system where the molten iron has its greatest kinetic energy. The molten iron is first caused to flow tangentially by the afflux plane of the ceramic filter and then is deflected to create turbulence directly before the afflux plane of the filter.
摘要翻译：公开了一种用于过滤铁水的陶瓷过滤器。陶瓷过滤器由具有开孔泡沫结构的高熔点陶瓷材料制成，过滤器的不同部分的可变堆积密度以及至少一个附着面。为了有效地过滤铁水，过滤器表面与过滤器体积的比例应在约0.0003至9m 2 / cm 3的范围内，特定过滤器阻力在流动下应在约0.1至0.9bar-cm的范围内速率为5立方米/小时，并且过滤器上的压力损失ΔΔTA应根据以下关系依赖于附着平面F的电阻率rho，滤波器长度和表面积：过滤方法还公开了使用该陶瓷过滤器的铁水。在该方法中，陶瓷过滤器位于铸铁系统中靠近熔融铁具有最大动能的点处。首先使铁水通过陶瓷过滤器的塌陷面切向流动，然后被偏转以在过滤器的附着平面之前直接产生湍流。

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