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51. 发明授权

US07464157B2 Information transmission system, information transmission method, electric device communication device, information communication device, communication control program 有权
标题翻译：信息传输系统，信息传输方式，电子设备通信设备，信息通信设备，通信控制程序
公开(公告)号：US07464157B2
公开(公告)日：2008-12-09
申请号：US10544453
申请日：2004-02-05
申请人： Takaaki Okude , Masafumi Sadahira , Yoshiaki Watanabe , Atsushi Nakayama
发明人： Takaaki Okude , Masafumi Sadahira , Yoshiaki Watanabe , Atsushi Nakayama
IPC分类号： G06F15/173 , G06F15/16 , G06F11/00 , G05B11/01
CPC分类号： H04L12/2818 , H04L12/2803 , H04L67/02 , H04L67/025 , H04L67/12 , H04L67/14 , H04L67/36 , H04L69/16 , H04L69/164 , H04L69/329 , H04L2012/2849 , H04L2012/285
摘要： An information transfer system includes an information panel which controls electrical equipment and includes a first transmission and reception section. The system also includes a server which is communicably connected via a network to the information panel and includes a second transmission and reception section and a trigger generation section which generates a communication request trigger for making a request to communicate with the information panel. The first transmission and reception section transmits information based on a UDP protocol periodically to the server, the second transmission and reception section receives the information based on the UDP protocol. When the communication request trigger is generated, the second transmission and reception section transmits request response information based on the UDP protocol or based on a TCP protocol to a transmission-origin address of the information.
摘要翻译：信息传送系统包括控制电气设备并包括第一发送和接收部分的信息面板。该系统还包括经由网络可通信地连接到信息面板的服务器，并且包括生成用于进行与信息面板通信的请求的通信请求触发的第二发送和接收部分和触发器生成部分。第一发送和接收部分周期性地向服务器发送基于UDP协议的信息，第二发送和接收部分基于UDP协议接收信息。当产生通信请求触发时，第二发送和接收部分将基于UDP协议或基于TCP协议的请求响应信息发送到该信息的发送起始地址。

52. 发明申请

US20080080295A1 EMBEDDED SEMICONDUCTOR MEMORY DEVICE HAVING SELF-TIMING CONTROL SENSE AMPLIFIER 审中-公开
标题翻译：具有自拍控制感应放大器的嵌入式半导体存储器件
公开(公告)号：US20080080295A1
公开(公告)日：2008-04-03
申请号：US11833054
申请日：2007-08-02
申请人： Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama , Hiroaki Nakano
发明人： Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama , Hiroaki Nakano
IPC分类号： G11C8/00
CPC分类号： G11C11/22 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C11/413
摘要： A semiconductor memory device includes a precharge unit to precharge a reference bit line and a selection bit line with the same potential, the selection bit line being connected to a target nonvolatile storage element from which data is to be read, a charge extraction unit to extract charges from the reference bit line and the selection bit line with the same current characteristic, a recharge unit which recharges the reference bit line with a current that is smaller than the charges extracted by the charge extraction unit, and a plurality of differential amplifiers which compare a potential of the reference bit line and a potential of the selection bit line with a reference potential. The semiconductor memory device further includes an output circuit which outputs data from the target nonvolatile storage element connected to the selection bit line, based on outputs of the differential amplifiers.
摘要翻译：半导体存储器件包括：预充电单元，用于对参考位线进行预充电和具有相同电位的选择位线，所述选择位线连接到要从其读取数据的目标非易失性存储元件，提取单元以提取来自参考位线的电荷和具有相同电流特性的选择位线;再充电单元，其以比电荷提取单元提取的电荷小的电流对参考位线进行充电;以及多个差分放大器，其比较参考位线的电位和具有参考电位的选择位线的电位。半导体存储器件还包括输出电路，其基于差分放大器的输出，从连接到选择位线的目标非易失性存储元件输出数据。

53. 发明授权

US07345179B2 Process for producing pyrrolidine derivative 失效
标题翻译：制备吡咯烷衍生物的方法
公开(公告)号：US07345179B2
公开(公告)日：2008-03-18
申请号：US10556043
申请日：2004-05-07
申请人： Atsushi Nakayama , Nobuo Machinaga , Yoshiyuki Yoneda , Masaki Setoguchi
发明人： Atsushi Nakayama , Nobuo Machinaga , Yoshiyuki Yoneda , Masaki Setoguchi
IPC分类号： C07F9/02
CPC分类号： C07D207/12
摘要： This invention provides an industrially useful process for producing 1,4-transcyclohexanecarboxylic acid derivative (1) which has excellent VLA-4 inhibitory action and safety, and an intermediate which is useful in such method. More particularly, this invention relates to a process for converting a compound of formula (I) into a compound of formula (VI) by the reaction scheme:
摘要翻译：本发明提供了具有优异的VLA-4抑制作用和安全性的1,4-反式环己烷羧酸衍生物（1）的工业上有用的方法和可用于该方法的中间体。更具体地，本发明涉及通过反应方案将式（I）化合物转化为式（VI）的化合物的方法：

54. 发明申请

US20080002504A1 SEMICONDUCTOR MEMORY DEVICE IN WHICH DATA IS STORED IN NONVOLATILE STATE, BY USING SEMICONDUCTOR ELEMENTS OF METAL OXIDE SEMICONDUCTOR (MOS) STRUCTURE 有权
标题翻译：通过使用金属氧化物半导体（MOS）结构的半导体元件，数据存储在非易失性存储器中的半导体存储器件
公开(公告)号：US20080002504A1
公开(公告)日：2008-01-03
申请号：US11738774
申请日：2007-04-23
申请人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
发明人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L27/101 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.
摘要翻译：半导体存储器件包括存储元件，第一数据线和第二数据线，第一选择晶体管和第二选择晶体管。存储元件包括MOS结构的半导体元件，其中当半导体元件中提供的绝缘膜通过施加电压而被分解时数据被编程。第一和第二数据线连接到读出放大器。第一选择晶体管被配置为将存储元件连接到第一数据线，以便将数据编程在存储元件中。第二选择晶体管被配置为将存储器元件连接到第二数据线，以便对存储元件中的数据进行编程，并检测存储元件中编程的数据。第二选择晶体管具有比第一选择晶体管小的栅电极宽度。

55. 发明申请

US20070054909A1 VLA-4 inhibitor compounds 审中-公开
公开(公告)号：US20070054909A1
公开(公告)日：2007-03-08
申请号：US11594432
申请日：2006-11-08
申请人： John Baldwin , Edward McDonald , Kevin Moriarty , Christopher Sarko , Nobuo Machinaga , Atsushi Nakayama , Jun Chiba , Shin Iimura , Yoshiyuki Yoneda
发明人： John Baldwin , Edward McDonald , Kevin Moriarty , Christopher Sarko , Nobuo Machinaga , Atsushi Nakayama , Jun Chiba , Shin Iimura , Yoshiyuki Yoneda
IPC分类号： A61K31/5375 , A61K31/496 , A61K31/4439 , A61K31/426 , A61K31/401 , A61K31/405 , C07D403/02
CPC分类号： C07D207/08 , C07C275/42 , C07C2601/02 , C07D207/09 , C07D207/12 , C07D207/14 , C07D207/16 , C07D207/22 , C07D207/24 , C07D209/12 , C07D211/26 , C07D211/34 , C07D211/38 , C07D213/55 , C07D217/02 , C07D277/04 , C07D277/28 , C07D277/48 , C07D295/13 , C07D295/185 , C07D307/33 , C07D311/20 , C07D401/06 , C07D401/12 , C07D401/14 , C07D403/02 , C07D413/06 , C07D491/04
摘要： Compounds that selectively inhibit the binding of ligands to α4β1 integrin (VLA-4) and methods for their preparation are disclosed. In one embodiment, compounds of the invention are represented by Formula I: As selective inhibitors of VLA-4 mediated cell adhesion, compounds of the present invention are useful in the treatment of conditions associated with such adhesion, including, but not limited to, such conditions as inflammatory and autoimmune responses, diabetes, asthma, psoriasis, inflammatory bowel disease, transplantation rejection, and tumor metastasis. Also disclosed are methods of inhibiting VLA-4 mediated cell adhesion and methods of treating conditions associated with LA-4 mediated cell adhesion.

56. 发明授权

US07157487B2 Vla-4 inhibitors 失效
标题翻译： Vla-4抑制剂
公开(公告)号：US07157487B2
公开(公告)日：2007-01-02
申请号：US10451159
申请日：2001-12-28
申请人： Atsushi Nakayama , Nobuo Machinaga , Yoshiyuki Yoneda , Yuichi Sugimoto , Jun Chiba , Toshiyuki Watanabe , Shin Iimura
发明人： Atsushi Nakayama , Nobuo Machinaga , Yoshiyuki Yoneda , Yuichi Sugimoto , Jun Chiba , Toshiyuki Watanabe , Shin Iimura
IPC分类号： A61K31/405 , C07D209/04
CPC分类号： C07D263/58 , C07C275/42 , C07D209/42 , C07D401/12 , C07D401/14 , C07D403/12 , C07D413/06 , C07D413/12 , C07D413/14 , C07D417/06 , C07D417/12 , C07D471/04 , C07D491/04
摘要： The present invention relates to a compound represented by the following formula (I): (wherein, W represents WA-A1-WB- (in which, WA is substituted or unsubstituted aryl, etc., A1 is —NR1—, single bond, —C(O)—, etc., and WB is substituted or unsubstituted arylene, etc.), R is single bond, —NH—, —OCH2—, alkenylene, etc., X is —C(O)—, —CH2—, etc., and M is, for example, the following formula: (in which, R11, R12 and R13 each independently represents hydrogen, hydroxyl, amino, halogen, etc., R14 is hydrogen or lower alkyl, Y represents —CH2—O—, etc., Z is substituted or unsubstituted arylene, etc., A2 is single bond, etc, and R10 is hydroxyl or lower alkoxy)), or salt thereof; and a medicament containing the same. This compound or salt thereof selectively inhibits binding of cell adhesion molecules to VLA-4 and exhibits high bioavailability so that it is useful as a preventive and/or remedy for inflammatory diseases, autoimmune diseases, metastasis, bronchial asthma, rhinostenosis, diabetes, and the like.
摘要翻译：本发明涉及由下式（I）表示的化合物：（其中，W表示W A，A，B， - （其中，W A是取代或未取代的芳基等，A 1是-NR 1 - 单键，-C （O） - 等，W B是取代或未取代的亚芳基等），R是单键，-NH-，-OCH 2 - ，亚烯基等等，X是-C（O） - ， - CH 2 - 等，M是例如下式：（其中R 11， R 12，R 12和R 13各自独立地表示氢，羟基，氨基，卤素等，R 14是氢或低级烷基，Y表示-CH 2 -O-O-等，Z是取代或未取代的亚芳基等，A 2是单键等，R“ 10是羟基或低级烷氧基））或其盐; 和含有该药物的药物。该化合物或其盐选择性地抑制细胞粘附分子与VLA-4的结合并且表现出高的生物利用度，使得其可用作炎性疾病，自身免疫性疾病，转移，支气管哮喘，鼻窦炎，糖尿病的预防和/或补救。喜欢。

57. 发明申请

US20060155841A1 Information transmission system, information transmission method, electric device communication device, information communication device, communication control program 有权
标题翻译：信息传输系统，信息传输方式，电子设备通信设备，信息通信设备，通信控制程序
公开(公告)号：US20060155841A1
公开(公告)日：2006-07-13
申请号：US10544453
申请日：2004-02-05
申请人： Takaaki Okude , Masafumi Sadahira , Yoshiaki Watanabe , Atsushi Nakayama
发明人： Takaaki Okude , Masafumi Sadahira , Yoshiaki Watanabe , Atsushi Nakayama
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L12/2818 , H04L12/2803 , H04L67/02 , H04L67/025 , H04L67/12 , H04L67/14 , H04L67/36 , H04L69/16 , H04L69/164 , H04L69/329 , H04L2012/2849 , H04L2012/285
摘要： The present invention relates to information transfer system, an information transfer method, an electrical-equipment communication apparatus, an information communication apparatus and a computer-readable record medium with a communication control program. An information panel 1 which controls electrical equipment 3 includes a first transmission and reception section 11, a server 2 which is communicably connected via a network 4 to the information panel 1 includes a transmission and reception section 21 and a trigger generation section 22 which generates a communication request trigger for making a request to communicate with the information panel 1, the first transmission and reception section 11 transmits information based on a UDP protocol periodically to the server 2, the transmission and reception section 21 receives the information based on the UDP protocol which is periodically transmitted and when the communication request trigger is generated, transmits request response information based on the UDP protocol or request response information based on a TCP protocol to the transmission-origin address of the information based on the UDP protocol.
摘要翻译：信息传输系统，信息传送方法，电气设备通信装置，信息通信装置以及具有通信控制程序的计算机可读记录介质技术领域本发明涉及信息传送系统，控制电气设备3的信息面板1包括第一发送和接收部分11，经由网络4可信地连接到信息面板1的服务器2包括发送和接收部分21以及触发器产生部分22，通信请求触发器，用于请求与信息面板1通信，第一发送和接收部分11根据UDP协议周期性地向服务器2发送信息，发送和接收部分21基于UDP协议接收信息周期性地发送，并且当生成通信请求触发时，基于UDP协议发送请求响应信息或者基于TCP协议向基于UDP协议的信息的发送起始地址请求响应信息。

58. 发明申请

US20060133167A1 Nonvolatile semiconductor memory device using irreversible storage elements 有权
标题翻译：使用不可逆存储元件的非易失性半导体存储器件
公开(公告)号：US20060133167A1
公开(公告)日：2006-06-22
申请号：US11231795
申请日：2005-09-22
申请人： Atsushi Nakayama , Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Osamu Wada
发明人： Atsushi Nakayama , Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Osamu Wada
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C17/16 , G11C17/18 , G11C29/027
摘要： A nonvolatile semiconductor memory device comprising a storage element which is programmed with information by varying electrical properties irreversibly, a selection switch connected in series to the storage element, a protection element connected in parallel to the storage element to protect the storage element from irreversible variations of electrical properties when the storage element is unprogrammed, a first activation circuit which activates the selection switch, a second activation circuit which activates the protection element in complement with the first activation circuit in normal mode, and a test circuit which conducts a test on the storage element while the second activation circuit is activating the protection element together with the first activation circuit in test mode.
摘要翻译：一种非易失性半导体存储器件，包括通过不可逆地改变电气特性而被编程的信息的存储元件，与存储元件串联连接的选择开关，与存储元件并联连接的保护元件，以保护存储元件免受不可逆变化的影响存储元件未编程时的电气特性，激活选择开关的第一激活电路，以正常模式激活与第一激活电路互补的保护元件的第二激活电路以及对存储器进行测试的测试电路而第二激活电路在测试模式下与第一激活电路一起激活保护元件。

59. 发明申请

US20060133127A1 Nonvolatile semiconductor memory device to which information can be written only once 有权
标题翻译：只能写入一次信息的非易失性半导体存储器件
公开(公告)号：US20060133127A1
公开(公告)日：2006-06-22
申请号：US11231983
申请日：2005-09-22
申请人： Hiroaki Nakano , Toshimasa Namekawa , Atsushi Nakayama , Osamu Wada , Hiroshi Ito
发明人： Hiroaki Nakano , Toshimasa Namekawa , Atsushi Nakayama , Osamu Wada , Hiroshi Ito
IPC分类号： G11C17/00 , G11C17/14 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： A nonvolatile semiconductor memory device having a storage element which is programmed with information by breaking an insulating film of the storage element, includes a cell array including a plurality of storage cells arranged in matrix, each of the storage cells having the storage element and a selection switch connected in series to the storage element, and a row selection control circuit which activates a row selection line connected to a given number of storage cells. The device further includes a write control circuit which controls a voltage of each of data lines bit by bit in accordance with write data, the data lines being connected to a given number of storage cells connected to the row selection line activated by the row selection control circuit.
摘要翻译：一种具有存储元件的非易失性半导体存储器件，其通过破坏存储元件的绝缘膜而被编程为信息，包括：具有矩阵排列的多个存储单元的单元阵列，每个存储单元具有存储元件和选择开关串联连接到存储元件;以及行选择控制电路，其激活连接到给定数量的存储单元的行选择线。该装置还包括写入控制电路，其根据写入数据逐位地控制数据线的电压，数据线连接到与行选择控制激活的行选择线连接的给定数量的存储单元电路。

60. 发明授权

US06734693B2 Semiconductor integrated circuit having a semiconductor storage circuit and a test circuit for testing the semiconductor storage circuit 失效
标题翻译：半导体集成电路具有半导体存储电路和用于测试半导体存储电路的测试电路
公开(公告)号：US06734693B2
公开(公告)日：2004-05-11
申请号：US10294788
申请日：2002-11-15
申请人： Atsushi Nakayama
发明人： Atsushi Nakayama
IPC分类号： G01R3102
CPC分类号： G11C29/56012 , G01R31/318558 , G01R31/318563 , G01R31/318572 , G11C29/48 , G11C2029/5602
摘要： A first test circuit is supplied with test signals to test an operation of a first semiconductor storage circuit. The test signals include a test input signal, a test output signal, and a test sync signal. A second test circuit receives the test signals from the first test circuit to test an operation of a second semiconductor storage circuit. The first test circuit uses the test input signal as information to operate the first semiconductor storage circuit in synchronization with the test sync signal and supplies the test input signal to the second test circuit. The first test circuit also synchronizes a signal, which is determined by performing a logical operation between the output of the first semiconductor storage circuit and the test output signal supplied thereto, with the test sync signal and supplies the signal to the second test circuit as a test output signal.
摘要翻译：向第一测试电路提供测试信号以测试第一半导体存储电路的操作。测试信号包括测试输入信号，测试输出信号和测试同步信号。第二测试电路从第一测试电路接收测试信号以测试第二半导体存储电路的操作。第一测试电路使用测试输入信号作为与测试同步信号同步地操作第一半导体存储电路的信息，并将测试输入信号提供给第二测试电路。第一测试电路还使通过在第一半导体存储电路的输出和所提供的测试输出信号之间的逻辑运算与测试同步信号进行逻辑运算而确定的信号同步，并将该信号作为第二测试电路提供测试输出信号。

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