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1. 发明授权

US07557400B2 Semiconductor device in which capacitance of a MOS capacitor is complemented with the capacitance of a wiring capacitor 有权
标题翻译： MOS电容器的电容与布线电容器的电容互补的半导体器件
公开(公告)号：US07557400B2
公开(公告)日：2009-07-07
申请号：US11670605
申请日：2007-02-02
申请人： Osamu Wada , Hiroaki Nakano , Hiroshi Ito , Toshimasa Namekawa , Atsushi Nakayama
发明人： Osamu Wada , Hiroaki Nakano , Hiroshi Ito , Toshimasa Namekawa , Atsushi Nakayama
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0222 , H01L2924/0002 , H02M3/073 , H01L2924/00
摘要： A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region of said MOS capacitor.
摘要翻译：半导体器件具有其中共同连接漏极区域和MOS结构的源极区域的MOS电容器，并且在共同连接的漏极区域/源极区域和MOS结构的栅极电极之间形成电容; 以及具有通过层间绝缘膜形成在所述MOS电容器上的第一梳状布线的布线电容器连接到所述MOS电容器的栅电极，并且具有突出部分，如梳齿形状突出，第二梳状通过层间绝缘膜在所述MOS电容器上形成的布线跨越与第一梳状布线的线间绝缘膜布置，连接到漏区和源极区，并且具有突出部分如梳齿突出，其中，所述第二梳状布线的突出部分与所述第一梳状布线的突出部分交替布置，并且垂直于连接所述MOS电容器的漏极区域和源极区域的沟道方向布置。

2. 发明申请

US20060158923A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060158923A1
公开(公告)日：2006-07-20
申请号：US11221943
申请日：2005-09-09
申请人： Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Atsushi Nakayama , Osamu Wada
发明人： Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Atsushi Nakayama , Osamu Wada
IPC分类号： G11C11/24
CPC分类号： G11C5/145 , G11C17/16 , G11C17/18
摘要： A nonvolatile semiconductor memory device includes a storage element which is programmed with information by breaking an insulating film by application of electrical stress to the storage element, a control switch which controls the application of electrical stress to the storage element, and a control circuit which controls conduction/nonconduction of the control switch. The device further includes a power supply circuit including a voltage generation circuit which generates a first voltage to cause the electrical stress in program operation, a sensing circuit which senses that the insulating film is broken down, and a counter circuit which controls the control circuit to interrupt the application of electrical stress to the storage element when a given period of time elapses after the sensing circuit senses that the insulating film is broken down.
摘要翻译：一种非易失性半导体存储器件，包括通过对存储元件施加电应力而破坏绝缘膜的信息来编程的存储元件，控制对存储元件施加电应力的控制开关，以及控制电路导通/非导通控制开关。该装置还包括电源电路，该电源电路包括产生第一电压以在编程操作中产生电应力的电压产生电路，感测绝缘膜分解的感测电路，以及控制电路控制到在感测电路感测到绝缘膜破裂之后经过给定的时间段时，中断对存储元件的电应力的施加。

3. 发明授权

US07613062B2 Semiconductor memory device in which data is stored in nonvolatile state, by using semiconductor elements of metal oxide semiconductor (MOS) structure 有权
标题翻译：通过使用金属氧化物半导体（MOS）结构的半导体元件，以非易失性状态存储数据的半导体存储器件
公开(公告)号：US07613062B2
公开(公告)日：2009-11-03
申请号：US11738774
申请日：2007-04-23
申请人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
发明人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L27/101 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.
摘要翻译：半导体存储器件包括存储元件，第一数据线和第二数据线，第一选择晶体管和第二选择晶体管。存储元件包括MOS结构的半导体元件，其中当半导体元件中提供的绝缘膜通过施加电压而被分解时数据被编程。第一和第二数据线连接到读出放大器。第一选择晶体管被配置为将存储元件连接到第一数据线，以便将数据编程在存储元件中。第二选择晶体管被配置为将存储器元件连接到第二数据线，以便对存储元件中的数据进行编程，并检测存储元件中编程的数据。第二选择晶体管具有比第一选择晶体管小的栅电极宽度。

4. 发明授权

US07599206B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07599206B2
公开(公告)日：2009-10-06
申请号：US12032110
申请日：2008-02-15
申请人： Atsushi Nakayama , Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Osamu Wada
发明人： Atsushi Nakayama , Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Osamu Wada
IPC分类号： G11C17/00 , G11C29/00 , G11C17/18
CPC分类号： G11C17/18
摘要： A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with a high voltage; a sense node having its one end connected to each of the anti-fuse elements; a sense amplifier comparing the potential of the sense node with the reference potential and amplifying the difference therebetween, the sense amplifier being activated according to a sense-amplifier activation signal; an initialization circuit initializing the potential of the sense node according to an initialization signal; a control circuit outputting the initialization signal at a predetermined timing after input of an external signal input from the outside and outputting a first activation signal to activate the sense amplifier at a predetermined timing after input of the external signal; and a switching circuit outputting the first activation signal as the sense-amplifier activation signal when a normal data read operation is performed, and outputting an inverted version of the external signal as the sense-amplifier activation signal when a test execution is instructed for the one or more memory cells before the gate insulation film is broken down.
摘要翻译：非挥发性半导体存储装置包括：一个或多个存储单元，包括能够通过以高电压分解MOS晶体管的栅极绝缘膜来写入数据的抗熔丝元件; 感测节点，其一端连接到每个反熔丝元件; 感测放大器将感测节点的电位与参考电位进行比较，并放大其间的差值，根据读出放大器激活信号来激活读出放大器; 初始化电路根据初始化信号初始化感测节点的电位; 控制电路在输入从外部输入的外部信号的输入之后的预定定时输出初始化信号，并输出第一激活信号，以在输入外部信号之后的预定定时激活读出放大器; 以及当执行正常数据读取操作时，输出作为读出放大器激活信号的第一激活信号的切换电路，并且当指示测试执行时，输出外部信号的反转版本作为读出放大器激活信号或更多的存储单元在栅极绝缘膜破裂之前。

5. 发明授权

US07505300B2 Nonvolatile semiconductor memory device using nonvolatile storage elements to which data can be written only once 有权
标题翻译：使用非易失性存储元件的非易失性半导体存储器件，数据只能写入一次
公开(公告)号：US07505300B2
公开(公告)日：2009-03-17
申请号：US11733933
申请日：2007-04-11
申请人： Toshimasa Namekawa , Hiroshi Ito , Hiroaki Nakano , Osamu Wada , Atsushi Nakayama
发明人： Toshimasa Namekawa , Hiroshi Ito , Hiroaki Nakano , Osamu Wada , Atsushi Nakayama
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and a write operation control circuit to which a write operation instruction signal is input asynchronously with the external input clock. The read operation instruction signal gives an instruction to start a read operation to read data out of the nonvolatile storage element, and the write operation instruction signal gives an instruction to start a write operation to write data to the nonvolatile storage element. The device further includes a reset circuit which resets an operation of the read operation control circuit upon receiving the write operation instruction signal.
摘要翻译：非易失性半导体存储器件包括禁止数据被重写的非易失性存储元件，与外部输入时钟同步地捕获读取操作指令信号的读取操作控制电路以及写入操作的写入操作控制电路指令信号与外部输入时钟异步输入。读取操作指令信号给出开始读取操作以从非易失性存储元件读出数据的指令，并且写入操作指令信号给出开始写入操作以将数据写入非易失性存储元件的指令。该装置还包括复位电路，其在接收到写入操作指令信号时复位读取操作控制电路的操作。

6. 发明授权

US07257012B2 Nonvolatile semiconductor memory device using irreversible storage elements 有权
标题翻译：使用不可逆存储元件的非易失性半导体存储器件
公开(公告)号：US07257012B2
公开(公告)日：2007-08-14
申请号：US11231795
申请日：2005-09-22
申请人： Atsushi Nakayama , Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Osamu Wada
发明人： Atsushi Nakayama , Toshimasa Namekawa , Hiroaki Nakano , Hiroshi Ito , Osamu Wada
IPC分类号： G11C17/00
CPC分类号： G11C29/02 , G11C17/16 , G11C17/18 , G11C29/027
摘要： A nonvolatile semiconductor memory device comprising a storage element which is programmed with information by varying electrical properties irreversibly, a selection switch connected in series to the storage element, a protection element connected in parallel to the storage element to protect the storage element from irreversible variations of electrical properties when the storage element is unprogrammed, a first activation circuit which activates the selection switch, a second activation circuit which activates the protection element in complement with the first activation circuit in normal mode, and a test circuit which conducts a test on the storage element while the second activation circuit is activating the protection element together with the first activation circuit in test mode.
摘要翻译：一种非易失性半导体存储器件，包括通过不可逆地改变电气特性而被编程的信息的存储元件，与存储元件串联连接的选择开关，与存储元件并联连接的保护元件，以保护存储元件免受不可逆变化的影响存储元件未编程时的电气特性，激活选择开关的第一激活电路，以正常模式激活与第一激活电路互补的保护元件的第二激活电路以及对存储器进行测试的测试电路而第二激活电路在测试模式下与第一激活电路一起激活保护元件。

7. 发明申请

US20070070693A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING STORAGE UNIT HAVING NONVOLATILE AND VOLATILE MEMORY ELEMENT SECTIONS 有权
标题翻译：半导体集成电路设备，包括具有非易失性存储元件部分的存储单元
公开(公告)号：US20070070693A1
公开(公告)日：2007-03-29
申请号：US11531118
申请日：2006-09-12
申请人： Hiroaki Nakano , Toshimasa Namekawa , Osamu Wada , Hiroshi Ito , Atsushi Nakayama
发明人： Hiroaki Nakano , Toshimasa Namekawa , Osamu Wada , Hiroshi Ito , Atsushi Nakayama
IPC分类号： G11C14/00
CPC分类号： G11C11/005 , G11C29/789 , G11C29/802
摘要： A semiconductor integrated circuit device includes a storage unit arranged on a semiconductor chip to store a plurality of data, and a plurality of registers provided on the semiconductor chip, the registers storing the data transferred from the storage unit, respectively. The storage unit has a nonvolatile memory element section and a volatile memory element section. The nonvolatile memory element section includes an address area which stores identification information of the registers as addresses and a data area which stores the data to correspond to the addresses by varying electrical characteristics irreversibly. The volatile memory element section temporarily stores the data read from the nonvolatile memory element section.
摘要翻译：一种半导体集成电路器件，包括布置在半导体芯片上以存储多个数据的存储单元和设置在半导体芯片上的多个寄存器，寄存器分别存储从存储单元传送的数据。存储单元具有非易失性存储元件部分和易失性存储元件部分。非易失性存储元件部分包括存储寄存器的识别信息作为地址的地址区域和通过不可逆地改变电气特性来存储对应于地址的数据的数据区域。易失性存储元件部临时存储从非易失性存储元件部读出的数据。

8. 发明授权

US07733713B2 Non-volatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07733713B2
公开(公告)日：2010-06-08
申请号：US11872281
申请日：2007-10-15
申请人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
发明人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
IPC分类号： G11C7/00
CPC分类号： G11C17/16 , G11C7/1006 , G11C17/18
摘要： A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.
摘要翻译：存储单元阵列包括多个非易失性半导体存储器元件，每个存储元件以非易失性方式存储数据。移位寄存器存储从半导体存储元件读取的数据，并将数据顺序地传送到外部，移位寄存器还存储从外部传送的数据，并将数据存储在半导体存储元件中。校正子产生电路连接到移位寄存器的输出端，校正子产生电路产生从输出端输出的数据的校正子。误差校正电路使用数据和校正子来纠正数据的错误。

9. 发明申请

US20080080295A1 EMBEDDED SEMICONDUCTOR MEMORY DEVICE HAVING SELF-TIMING CONTROL SENSE AMPLIFIER 审中-公开
标题翻译：具有自拍控制感应放大器的嵌入式半导体存储器件
公开(公告)号：US20080080295A1
公开(公告)日：2008-04-03
申请号：US11833054
申请日：2007-08-02
申请人： Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama , Hiroaki Nakano
发明人： Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama , Hiroaki Nakano
IPC分类号： G11C8/00
CPC分类号： G11C11/22 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C11/413
摘要： A semiconductor memory device includes a precharge unit to precharge a reference bit line and a selection bit line with the same potential, the selection bit line being connected to a target nonvolatile storage element from which data is to be read, a charge extraction unit to extract charges from the reference bit line and the selection bit line with the same current characteristic, a recharge unit which recharges the reference bit line with a current that is smaller than the charges extracted by the charge extraction unit, and a plurality of differential amplifiers which compare a potential of the reference bit line and a potential of the selection bit line with a reference potential. The semiconductor memory device further includes an output circuit which outputs data from the target nonvolatile storage element connected to the selection bit line, based on outputs of the differential amplifiers.
摘要翻译：半导体存储器件包括：预充电单元，用于对参考位线进行预充电和具有相同电位的选择位线，所述选择位线连接到要从其读取数据的目标非易失性存储元件，提取单元以提取来自参考位线的电荷和具有相同电流特性的选择位线;再充电单元，其以比电荷提取单元提取的电荷小的电流对参考位线进行充电;以及多个差分放大器，其比较参考位线的电位和具有参考电位的选择位线的电位。半导体存储器件还包括输出电路，其基于差分放大器的输出，从连接到选择位线的目标非易失性存储元件输出数据。

10. 发明申请

US20080002504A1 SEMICONDUCTOR MEMORY DEVICE IN WHICH DATA IS STORED IN NONVOLATILE STATE, BY USING SEMICONDUCTOR ELEMENTS OF METAL OXIDE SEMICONDUCTOR (MOS) STRUCTURE 有权
标题翻译：通过使用金属氧化物半导体（MOS）结构的半导体元件，数据存储在非易失性存储器中的半导体存储器件
公开(公告)号：US20080002504A1
公开(公告)日：2008-01-03
申请号：US11738774
申请日：2007-04-23
申请人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
发明人： Hiroaki Nakano , Toshimasa Namekawa , Hiroshi Ito , Osamu Wada , Atsushi Nakayama
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L27/101 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.
摘要翻译：半导体存储器件包括存储元件，第一数据线和第二数据线，第一选择晶体管和第二选择晶体管。存储元件包括MOS结构的半导体元件，其中当半导体元件中提供的绝缘膜通过施加电压而被分解时数据被编程。第一和第二数据线连接到读出放大器。第一选择晶体管被配置为将存储元件连接到第一数据线，以便将数据编程在存储元件中。第二选择晶体管被配置为将存储器元件连接到第二数据线，以便对存储元件中的数据进行编程，并检测存储元件中编程的数据。第二选择晶体管具有比第一选择晶体管小的栅电极宽度。

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