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51. 发明申请

US20120180010A1 METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE 有权
标题翻译：使用低温退火工艺制造器件的方法，器件和设计结构
公开(公告)号：US20120180010A1
公开(公告)日：2012-07-12
申请号：US13421400
申请日：2012-03-15
申请人： Anthony G. DOMENICUCCI , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. DOMENICUCCI , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译：提供了使用退火处理序列制造器件的方法。更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

52. 发明授权

US07851376B2 Compressive nitride film and method of manufacturing thereof 有权
标题翻译：压缩性氮化物膜及其制造方法
公开(公告)号：US07851376B2
公开(公告)日：2010-12-14
申请号：US12364088
申请日：2009-02-02
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

53. 发明申请

US20090181544A1 METHOD FOR PREVENTING BACKSIDE DEFECTS IN DIELECTRIC LAYERS FORMED ON SEMICONDUCTOR SUBSTRATES 有权
标题翻译：用于防止在半导体衬底上形成的电介质层中的背面缺陷的方法
公开(公告)号：US20090181544A1
公开(公告)日：2009-07-16
申请号：US11972895
申请日：2008-01-11
申请人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
发明人： Chester T. Dziobkowski , Thomas F. Houghton , Emily Kinser , Darryl D. Restaino , Yun-Yu Wang
IPC分类号： H01L21/311
CPC分类号： H01L21/31612 , C23C16/325 , C23C16/505 , C23C16/56 , H01L21/02131 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/3145 , H01L21/3148 , H01L21/31629
摘要： A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.
摘要翻译：在形成在衬底上的氮掺杂碳化硅或氮掺杂氢化碳化硅层上形成TEOS氧化物层的方法。该方法包括在靠近衬底顶表面的顶表面和顶侧倾斜边缘上形成氮掺杂碳化硅或氮掺杂氢化碳化硅层; 去除或阻止在靠近基底的底表面的底侧斜边缘区域上形成富碳层，或将富碳层转化为氮掺杂碳化硅或氮掺杂氢化碳化硅; 以及在所述基板的顶面，顶侧倾斜边缘和底侧斜边缘区域上形成TEOS氧化物层。

54. 发明授权

US07560692B2 Method of TEM sample preparation for electron holography for semiconductor devices 失效
标题翻译：半导体器件电子全息术的TEM样品制备方法
公开(公告)号：US07560692B2
公开(公告)日：2009-07-14
申请号：US11617386
申请日：2006-12-28
申请人： Keith E. Barton , Steven H. Boettcher , John G. Gaudiello , Leon J. Kimball , Yun-Yu Wang
发明人： Keith E. Barton , Steven H. Boettcher , John G. Gaudiello , Leon J. Kimball , Yun-Yu Wang
IPC分类号： G01N1/32 , G01N23/04
CPC分类号： G01N1/2806
摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
摘要翻译：适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。这导致样品制备过程的改进的控制和产率。

55. 发明申请

US20090137109A1 COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：压电式薄膜及其制造方法
公开(公告)号：US20090137109A1
公开(公告)日：2009-05-28
申请号：US12364088
申请日：2009-02-02
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/71
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

56. 发明申请

US20090119357A1 ADVANCED CORRELATION AND PROCESS WINDOW EVALUATION APPLICATION 审中-公开
标题翻译：先进的关联和过程窗口评估应用
公开(公告)号：US20090119357A1
公开(公告)日：2009-05-07
申请号：US11934914
申请日：2007-11-05
申请人： James P. Rice , Yunsheng Song , Yun-Yu Wang , Chienfan Yu
发明人： James P. Rice , Yunsheng Song , Yun-Yu Wang , Chienfan Yu
IPC分类号： G06F17/15
CPC分类号： G06K9/6253
摘要： A method only has the user input (or select) a data type, a report key, a dependent variable table, and/or filtering restrictions. Using this information, the method automatically locates independent variable data based on the data type and the report key. This independent variable data can be in the form of a table and comprises independent variables. The method automatically joins the dependent variable table and the independent variable data to create a joint table. Then, the method can automatically perform a statistical analysis of the joint table to find correlations between the dependent variables and the independent variables and output the correlations, without requiring the user to input or identify the independent variables.
摘要翻译：方法只有用户输入（或选择）数据类型，报告键，因变量表和/或过滤限制。使用该信息，该方法根据数据类型和报告密钥自动定位独立的变量数据。这个独立的变量数据可以是一个表格的形式，并且包括自变量。该方法自动连接因变量表和独立变量数据以创建联合表。然后，该方法可以自动执行联合表的统计分析，以找出因变量和独立变量之间的相关性，并输出相关性，而不需要用户输入或识别自变量。

57. 发明授权

US07504337B2 IC chip uniform delayering methods 失效
标题翻译： IC芯片均匀推迟方法
公开(公告)号：US07504337B2
公开(公告)日：2009-03-17
申请号：US11690432
申请日：2007-03-23
申请人： Keith E. Barton , Thomas A. Bauer , Stanley J. Klepeis , John A. Miller , Yun-Yu Wang
发明人： Keith E. Barton , Thomas A. Bauer , Stanley J. Klepeis , John A. Miller , Yun-Yu Wang
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： G01N1/32 , H01L22/24
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译：公开了均匀地延迟IC芯片的方法。一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。

58. 发明申请

US20090039447A1 FET Device with Stabilized Threshold Modifying Material 有权
标题翻译：具有稳定阈值修改材料的FET器件
公开(公告)号：US20090039447A1
公开(公告)日：2009-02-12
申请号：US11834641
申请日：2007-08-06
申请人： Matthew W. Copel , Bruce B. Doris , Vijay Narayanan , Yun-Yu Wang
发明人： Matthew W. Copel , Bruce B. Doris , Vijay Narayanan , Yun-Yu Wang
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/513 , H01L21/28026 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/7833
摘要： A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.
摘要翻译：公开了一种用于制造FET器件的方法。 FET器件具有具有高k电介质部分的栅极绝缘体和阈值修饰材料。该方法将稳定材料引入栅极绝缘体中，以便阻止来自阈值修饰材料的一种或多种金属穿过栅极绝缘体的高k部分。稳定材料的引入可以包括在包含一种或多种金属的氧化物的层上设置稳定剂。稳定材料也可以并入高k电介质中。该方法的应用可能导致具有独特栅极绝缘体结构的FET器件。

59. 发明申请

US20080020535A1 SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
标题翻译：减少应力和改进的栅格电阻的硅胶结构和工艺
公开(公告)号：US20080020535A1
公开(公告)日：2008-01-24
申请号：US11866751
申请日：2007-10-03
申请人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
发明人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/665
摘要： A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.
摘要翻译：一种硅化物盖结构和制造具有低薄层电阻的硅化物盖的方法。该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

60. 发明申请

US20070269992A1 COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：压电式薄膜及其制造方法
公开(公告)号：US20070269992A1
公开(公告)日：2007-11-22
申请号：US11419217
申请日：2006-05-19
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/31 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2和5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

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