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51. 发明授权

US06806572B2 Structure for contact formation using a silicon-germanium alloy 失效
标题翻译：使用硅 - 锗合金的接触形成结构
公开(公告)号：US06806572B2
公开(公告)日：2004-10-19
申请号：US10277688
申请日：2002-10-22
申请人： Randhir P. S. Thakur
发明人： Randhir P. S. Thakur
IPC分类号： H01L2334
CPC分类号： H01L21/76831 , H01L21/28525 , H01L21/76802 , H01L21/76843 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76879 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.
摘要翻译：提供了一种使用掺杂硅改善接触的新方法和结构。这些结构被集成到几个较高级别的实施例中。改进的接触具有低接触电阻率。因此，在IGFET器件和随后的金属化层之间提供改进的结。通过使用硅 - 锗（Si-Ge）合金获得改进。该合金可以通过将锗沉积到基底上并随后对接触进行退火或通过选择性地将预成型合金沉积到接触开口中而形成。上述优点结合相对较少的工艺步骤。

52. 发明授权

US06787482B2 Method to form a DRAM capacitor using low temperature reoxidation 失效
标题翻译：使用低温再氧化形成DRAM电容器的方法
公开(公告)号：US06787482B2
公开(公告)日：2004-09-07
申请号：US10223004
申请日：2002-08-14
申请人： Randhir P. S. Thakur , Brett Rolfson
发明人： Randhir P. S. Thakur , Brett Rolfson
IPC分类号： H01L2131
CPC分类号： H01L21/31604 , H01L21/31691 , H01L21/3185 , H01L28/82
摘要： An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an ultraviolet/ozone mixture, an ambient containing an ozone or an ambient containing an NF3/ozone mixture.
摘要翻译：本发明的实施例教导了用于半导体器件制造的晶片簇工具中的电容器电介质，该方法通过以下步骤形成：通过快速热氮化形成邻近层的氮化物; 以及使所述氮化物经受臭氧环境，其中所述臭氧环境选自含有紫外线/臭氧混合物的环境，含有臭氧的环境或含有NF 3 /臭氧混合物的环境。

53. 发明授权

US06730584B2 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures 有权
标题翻译：用于形成字线，晶体管栅极和导电互连以及字线，晶体管栅极和导电互连结构的方法
公开(公告)号：US06730584B2
公开(公告)日：2004-05-04
申请号：US09333770
申请日：1999-06-15
申请人： Klaus Florian Schuegraf , Carl Powell , Randhir P. S. Thakur
发明人： Klaus Florian Schuegraf , Carl Powell , Randhir P. S. Thakur
IPC分类号： H01L2122
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28273 , H01L29/4916
摘要： The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.
摘要翻译：本发明包括堆叠的半导体器件，包括栅极堆叠，字线，PROM，导电互连线以及用于形成这种结构的方法。本发明还包括一种形成晶体管栅极的方法，包括：a）形成栅极介电层; b）在所述栅极介电层上形成多晶硅栅极层; 以及c）用导电性增强掺杂剂掺杂多晶硅栅极层，所述掺杂剂以所述多晶硅层内的浓度梯度提供，所述浓度梯度在朝向所述栅极介电层的方向上增加。本发明还包括字线，包括：a）多晶硅线; 多晶硅线上的基本上不透氟的阻挡层; 以及b）基本上不透氟化阻挡层上的金属硅化物层。

54. 发明授权

US06703690B2 Apparatus for reducing isolation stress in integrated circuits 失效
标题翻译：降低集成电路隔离应力的方法和装置
公开(公告)号：US06703690B2
公开(公告)日：2004-03-09
申请号：US10188472
申请日：2002-07-02
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332
摘要： Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.
摘要翻译：通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小机械应力。通过改变氮化硅中的硅含量来实现分级。氮化硅可以以基本线性或非线性方式分级。在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小应力。在另一个实施例中，通过在衬底层上形成氮化硅来降低应力，衬底层又形成在基底层上。

55. 发明授权

US06682970B1 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer 有权
标题翻译：具有阻挡层电极和改进的阻挡层的电容器/反熔丝结构
公开(公告)号：US06682970B1
公开(公告)日：2004-01-27
申请号：US09692897
申请日：2000-10-19
申请人： Randhir P. S. Thakur , Garry A. Mercaldi , Michael Nuttall
发明人： Randhir P. S. Thakur , Garry A. Mercaldi , Michael Nuttall
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , G11C11/404 , G11C17/16 , H01L21/28568 , H01L21/76888 , H01L27/1085 , H01L27/11507 , H01L28/60 , H01L28/84
摘要： A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier material.
摘要翻译：半导体结构包括具有第一和第二相对侧的电介质层。导电层与电介质层的第一侧相邻并且耦合到第一端子，并且导电阻挡层与电介质层的第二侧相邻并耦合到第二端子。导电阻挡层可以由氮化钨，氮化钨，氮化钛或其它阻挡材料形成。

56. 发明授权

US06518121B2 Boride electrodes and barriers for cell dielectrics 有权
公开(公告)号：US06518121B2
公开(公告)日：2003-02-11
申请号：US09941759
申请日：2001-08-30
申请人： Husam N. Al-Shareef , Scott J. DeBoer , Dan Gealy , Randhir P. S. Thakur
发明人： Husam N. Al-Shareef , Scott J. DeBoer , Dan Gealy , Randhir P. S. Thakur
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L21/28568 , H01L27/10811 , H01L27/10888 , H01L28/60
摘要： Titanium boride (TiBx), zirconium boride (ZrBx) and hafnium boride (HfBx) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.

57. 发明授权

US06486020B1 High pressure reoxidation/anneal of high dielectric constant materials 有权
标题翻译：高介电常数材料的高压再氧化/退火
公开(公告)号：US06486020B1
公开(公告)日：2002-11-26
申请号：US09651377
申请日：2000-08-29
申请人： Randhir P. S. Thakur , Scott Jeffrey DeBoer
发明人： Randhir P. S. Thakur , Scott Jeffrey DeBoer
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/32105 , H01L21/3211 , H01L27/1085 , H01L28/84
摘要： A high dielectric constant (DC) capacitive dielectric film is fabricated in a capacitor structure using relatively high pressure surface treatments. After forming the DC capacitive dielectric film on a supporting bottom plate electrode structure, a surface treatment comprising oxidation, at a pressure of at least approximately one atmosphere and temperatures of approximately at least 200 degrees Celsius densities/conditions the HDC capacitive dielectric film. When using a polysilicon, crystalline silicon, hemispherical grain polysilicon, germanium, or silicon-germanium bottom plate electrode, a relatively high pressure surface treatment, comprising rapid thermal nitridation or oxidation, is used after forming the bottom plate electrode, forming a diffusion barrier layer in a controlled manner.
摘要翻译：使用相对较高压力的表面处理，在电容器结构中制造高介电常数（DC）电容电介质膜。在支撑底板电极结构上形成DC电容电介质膜之后，在至少约一个气压的压力和大约至少200摄氏度的温度的温度下，包括氧化的表面处理/使HDC电容性电介质膜变形。当使用多晶硅，晶体硅，半球形晶粒多晶硅，锗或硅锗底板电极时，在形成底板电极之后使用包括快速热氮化或氧化的相对高压表面处理，形成扩散阻挡层以受控的方式。

58. 发明授权

US06476433B1 Semiconductor interconnection structure and method 有权
标题翻译：具有同时形成的电极和互连层的半导体存储器件
公开(公告)号：US06476433B1
公开(公告)日：2002-11-05
申请号：US09655934
申请日：2000-09-06
申请人： Jeff Wu , Randhir P. S. Thakur
发明人： Jeff Wu , Randhir P. S. Thakur
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/76838 , H01L27/1052 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L28/60
摘要： A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material.
摘要翻译：存储单元阵列中的电容器下电极和外围电路内的第一互连层的同时由同一导电材料提供的存储器件和方法。外围电路中的电容器上电极和第二互连层也由相同的导电材料同时提供。

59. 发明授权

US06462394B1 Device configured to avoid threshold voltage shift in a dielectric film 失效
标题翻译：器件被配置为避免电介质膜中的阈值电压偏移
公开(公告)号：US06462394B1
公开(公告)日：2002-10-08
申请号：US09312373
申请日：1999-05-13
申请人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L2900
CPC分类号： H01L23/564 , H01L21/3144 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

60. 发明授权

US06426306B1 Barrier layer fabrication methods 有权
标题翻译：阻隔层制造方法
公开(公告)号：US06426306B1
公开(公告)日：2002-07-30
申请号：US09713845
申请日：2000-11-15
申请人： Scott J. Deboer , Randhir P. S. Thakur
发明人： Scott J. Deboer , Randhir P. S. Thakur
IPC分类号： H01L2131
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/1085 , H01L28/55 , H01L28/60
摘要： A process for forming a storage capacitor for a semiconductor assembly, by forming a first storage electrode having a top surface consisting of titanium nitride; forming a barrier layer directly on the titanium nitride, the barrier layer (a material containing any one of amorphous silicon, tantalum, titanium, or strontium) being of sufficient thickness to substantially limit the oxidation of the titanium nitride when the semiconductor assembly is subjected to an oxidizing agent (either an oxidizing agent or an nitridizing agent); converting a portion of the barrier layer to a dielectric compound; depositing a storage cell dielectric directly on the dielectric compound, the storage cell dielectric being of the same chemical makeup as the dielectric compound and thereby using the dielectric compound as a nucleation surface; and forming a second capacitor electrode on the storage cell dielectric.
摘要翻译：一种用于形成半导体组件的存储电容器的方法，其特征在于，形成具有由氮化钛组成的顶表面的第一存储电极; 在氮化钛上直接形成阻挡层，阻挡层（含有非晶硅，钽，钛或锶中的任何一种的材料）具有足够的厚度，以在半导体组件经受时基本上限制氮化钛的氧化氧化剂（氧化剂或氮化剂）; 将阻挡层的一部分转变为电介质化合物; 将存储单元电介质直接沉积在电介质化合物上，储能单元电介质具有与电介质化合物相同的化学组成，从而使用电介质化合物作为成核面; 以及在所述存储单元电介质上形成第二电容器电极。

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