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    • 53. 发明授权
      US4648174A Method of making high breakdown voltage semiconductor device 失效
    • Method of making high breakdown voltage semiconductor device
    • 制造高耐压半导体器件的方法
    • US4648174A
    • 1987-03-10
    • US698495
    • 1985-02-05
    • Victor A. K. Temple , Wirojana Tantraporn
    • Victor A. K. Temple , Wirojana Tantraporn
    • H01L21/033 , H01L29/06 , H01L21/26
    • H01L21/0334 , H01L29/0615 , H01L29/0688 , Y10S148/106 , Y10S148/145
    • A multiple-zone junction termination extension region is formed adjacent a reverse-blocking junction in a semiconductor device to increase the breakdown voltage of such device. A single mask is used to form the multiple-zone JTE region, with the mask having different patterns of openings in the different zones of the mask. Adjacent openings are maintained with a center-to-center spacing of less than 25 percent of the depletion width of the reverse-blocking junction in a voltage-supporting semiconductor layer adjoining the reverse-blocking junction at the ideal breakdown voltage of the junction. As a consequence, the resulting non-uniformities in doping of the various zones of the JTE region are negligibly small. An alternative JTE region is finely-graduated in dopant level from one end of the region to the other, as opposed to having multiple zones of discrete doping levels.
    • 在半导体器件中与反向阻挡结相邻的多区域结终止延伸区域形成以增加这种器件的击穿电压。 使用单个掩模来形成多区域JTE区域，其中掩模在掩模的不同区域中具有不同的开口图案。 维持相邻的开口，其中心到中心的间隔小于在结的理想击穿电压下邻接反向阻挡结的电压支撑半导体层中的反向阻挡结的耗尽宽度的25％。 因此，由此引起的JTE地区各个地区的不均匀性不可忽视。 与另外的区域的多个区域相反，替代的JTE区域以掺杂剂水平从该区域的一端细分为另一个。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 55. 发明授权
      US4466176A Process for manufacturing insulated-gate semiconductor devices with integral shorts 失效
    • Process for manufacturing insulated-gate semiconductor devices with integral shorts
    • 制造具有整体短路的绝缘栅半导体器件的工艺
    • US4466176A
    • 1984-08-21
    • US502834
    • 1983-06-09
    • Victor A. K. Temple
    • Victor A. K. Temple
    • H01L21/033 , H01L21/331 , H01L21/332 , H01L21/336 , H01L21/768 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H01L21/223 , H01L21/265
    • H01L29/7802 , H01L21/033 , H01L21/2855 , H01L29/41716 , H01L29/66333 , H01L29/66378 , H01L29/7395 , H01L29/7455 , H01L29/749 , H01L29/41766
    • Process for manufacturing insulated-gate semiconductor devices such as MOSFETs being with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. A two-stage polysilicon etch procedure is disclosed. The initial etch produces relatively narrow channels with substantially vertical sidewalls. Unetched portions of the polysilicon layer are used as masks during a first P type diffusion to form a shorting extension of the device base region and during the forming of a silicon nitride mask layer by a highly directional process, such as ion implantation, which avoids the formation of any nitride layer on the channel sidewalls. In a subsequent lateral etch step, previously unetched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures. These structures extend upwardly from and are spaced along the principal surface, and are also spaced from the silicon nitride masks. Then, the silicon nitride masks are each used as a combination diffusion and selective oxidation mask to form MOSFET source and base regions and to oxidize the polysilicon gate electrode sidewalls. The silicon nitride mask is removed, and appropriate electrode metallization applied.
    • 用于制造诸如MOSFET的绝缘栅半导体器件的工艺，其中半导体晶片（例如硅）包括漏极区域，初始均匀地形成在漏极区域的表面上的栅极绝缘层，以及多晶硅导电栅极层。 公开了两阶段多晶硅蚀刻工艺。 初始蚀刻产生具有基本垂直侧壁的相对窄的通道。 多晶硅层的未蚀刻部分在第一P型扩散期间用作掩模，以形成器件基极区域的短路延伸，以及在通过高度定向的工艺（例如离子注入）形成氮化硅掩模层期间，避免了 在通道侧壁上形成任何氮化物层。 在随后的横向蚀刻步骤中，蚀刻多晶硅栅极电极层的先前未蚀刻的部分以限定绝缘的多晶硅栅电极结构。 这些结构从主表面向上延伸并且沿着主表面间隔开，并且还与氮化硅掩模间隔开。 然后，将氮化硅掩模各自用作组合扩散和选择性氧化掩模，以形成MOSFET源极和基极区域并氧化多晶硅栅电极侧壁。 去除氮化硅掩模，并施加适当的电极金属化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 56. 发明授权
      US4430792A Minimal mask process for manufacturing insulated-gate semiconductor devices with integral shorts 失效
    • Minimal mask process for manufacturing insulated-gate semiconductor devices with integral shorts
    • 用于制造具有整体短路的绝缘栅半导体器件的最小掩模工艺
    • US4430792A
    • 1984-02-14
    • US406738
    • 1982-08-09
    • Victor A. K. Temple
    • Victor A. K. Temple
    • H01L21/28 , H01L21/331 , H01L21/336 , H01L29/749 , H01L21/265
    • H01L29/66712 , H01L21/28 , H01L29/66333 , H01L29/749
    • Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein the source and base regions and the source-to-base ohmic short are formed employing self-aligned masking techniques are disclosed. In the exemplary case of a MOSFET, the processes begin with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer at least to the drain region. The un-etched portions define polysilicon gate electrodes spaced along the drain region. A two-stage polysilicon etch procedure is disclosed. An initial etch step produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form a shorting extension of the device base region, preferably by ion implantation. In a subsequent lateral etch step, previously un-etched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures extending upwardly from and spaced along the principal surface. MOSFET source and base regions are then formed, preferably by vertical ion implantation, employing the polysilicon gate electrode structures as masks. Appropriate electrode metallization is applied.
    • 公开了用于制造绝缘栅半导体器件（例如MOSFET）的工艺，其中使用自对准掩蔽技术形成源极和基极区域以及源极 - 基极欧姆短路。 在MOSFET的示例性情况下，该工艺从包括漏极区域，初始在漏极区域的表面上均匀形成的栅极绝缘层和多晶硅导电栅极层的半导体晶片（例如硅）开始。 通过随后的掩模和技术步骤，至少通过漏极区域通过多晶硅栅极层蚀刻通道。 未蚀刻部分限定沿着漏极区域间隔开的多晶硅栅电极。 公开了两阶段多晶硅蚀刻工艺。 初始蚀刻步骤产生相对窄的通道。 然后将多晶硅层的未蚀刻部分用作掩模以优选通过离子注入形成器件基极区域的短路延伸。 在随后的横向蚀刻步骤中，蚀刻多晶硅栅极电极层的先前未蚀刻部分以限定从主表面向上延伸并且沿着主表面间隔开的绝缘多晶硅栅电极结构。 然后优选通过垂直离子注入形成MOSFET源极和基极区域，采用多晶硅栅电极结构作为掩模。 应用适当的电极金属化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 57. 发明授权
      US4352118A Thyristor with segmented turn-on line for directing turn-on current 失效
    • Thyristor with segmented turn-on line for directing turn-on current
    • 晶闸管采用分段导通线，用于引导导通电流
    • US4352118A
    • 1982-09-28
    • US240855
    • 1981-03-05
    • Victor A. K. Temple
    • Victor A. K. Temple
    • H01L29/10 , H01L29/417 , H01L29/423 , H01L29/74
    • H01L29/41716 , H01L29/102 , H01L29/42308
    • A thyristor with a segmented turn-on line is provided in which portions of the turn-on line are covered by boundary shorts formed by the emitter electrode extending over the emitter-base junction into contact with the thyristor base zone. The portions of the emitter-base junction between the boundary shorts constitute turn-on segments along which gated thyristor turn-on can occur. A gate current source is provided for supplying carriers to the base zone. The thyristor includes means for directing carriers supplied by the gate current source to the turn-on segments. In operation, initial thyristor turn-on occurs only along the turn-on segments, thereby shortening the length of the thyristor turn-on line and increasing gate sensitivity. Preferably, the turn-on segments are spaced regularly along the emitter-base junction to permit adjacent "on" areas to rapidly merge. In the preferred embodiment, the means for directing carriers to the turn-on segments includes a gate barrier region adjacent the base zone and of opposite conductivity type. The gate barrier region establishes isolated areas of contact between a gate electrode and the base, the areas of contact being generally aligned with the turn-on segments.
    • 提供具有分段导通线的晶闸管，其中导通线的部分被由在发射极 - 基极结上延伸的发射极形成的边界短路覆盖，与晶闸管基极区接触。 边界短路之间的发射极 - 基极结的部分构成了可以发生栅极晶闸管导通的导通段。 提供栅极电流源以将载体供应到基极区。 晶闸管包括用于将由栅极电流源提供的载流子引导到导通段的装置。 在操作中，初始晶闸管导通仅沿着导通段发生，从而缩短晶闸管导通线的长度并增加栅极灵敏度。 优选地，导通段沿着发射极 - 基极交界处规则地间隔开，以允许相邻的“开”区域快速合并。 在优选实施例中，用于将载体引导到导通段的装置包括邻近基极区并具有相反导电类型的栅极阻挡区。 栅极阻挡区域在栅电极和基极之间建立隔离的接触区域，接触区域通常与导通段对准。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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