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51. 发明授权

US07594216B2 Method and system for forming a mask pattern, method of manufacturing a semiconductor device, system forming a mask pattern on data, cell library and method of forming a photomask 失效
标题翻译：用于形成掩模图案的方法和系统，制造半导体器件的方法，在数据上形成掩模图案的系统，单元库和形成光掩模的方法
公开(公告)号：US07594216B2
公开(公告)日：2009-09-22
申请号：US10933334
申请日：2004-09-03
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , H01J37/3026 , H01J2237/31769
摘要： A method of forming a mask pattern comprises the following steps. A second cell library is prepared by making process proximity effect correction with respect to cell patterns stored in a first cell library. The second cell library stores corrected cell patterns. A first corrected cell pattern and a second corrected cell pattern of the corrected cell patterns are placed so that an edge of the first corrected cell pattern and an edge of the second corrected cell pattern contact or come close to or overlap each other. A boundary pattern at the boundary neighborhood between the first corrected cell pattern and the second corrected cell pattern is extracted. Process proximity effect correction is made with respect to the boundary pattern.
摘要翻译：形成掩模图案的方法包括以下步骤。通过相对于存储在第一个细胞库中的细胞图案进行过程接近效应校正来制备第二个细胞库。第二个细胞库存储校正的细胞图案。放置经校正的单元图案的第一校正单元图案和第二校正单元图形，使得第一校正单元图案的边缘和第二校正单元图案的边缘彼此接近或重叠。提取在第一校正单元图案和第二校正单元图案之间的边界邻域处的边界图案。相对于边界图案进行过程接近效应校正。

52. 发明授权

US07530049B2 Mask manufacturing system, mask data creating method and manufacturing method of semiconductor device 失效
标题翻译：掩模制造系统，掩模数据创建方法和半导体器件的制造方法
公开(公告)号：US07530049B2
公开(公告)日：2009-05-05
申请号：US11440086
申请日：2006-05-25
申请人： Sachiko Kobayashi , Toshiya Kotani
发明人： Sachiko Kobayashi , Toshiya Kotani
IPC分类号： G06F17/50
CPC分类号： G03F1/68 , G03F1/36
摘要： A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing system comprising a storage device storing processing data for semiconductor integrated circuits processed in the past, a plurality of operation processing modules, a module selecting section selecting at least one operation processing modules, an optical proximity effect correction section executing optical proximity effect correction to a processing object data and generating a correction data by utilizing past correction information applied for a stored data equivalent to the processing object data, a converting section converting the processing object data into mask data, and a drawing system drawing a mask pattern based on the mask data.
摘要翻译：掩模制造系统和掩模数据创建方法重复利用用于处理信息和环境的数据以减少光掩模生长期，以及半导体器件的制造方法。根据本发明的一个方面，提供了一种掩模制造系统，包括存储用于过去处理的半导体集成电路的处理数据的存储装置，多个操作处理模块，模块选择部分，其选择至少一个操作处理模块光学接近效应校正部分，对处理对象数据执行光学邻近效应校正，并通过利用应用于与处理对象数据相当的存储数据的过去校正信息产生校正数据;转换部分，将处理对象数据转换成掩模数据以及基于掩模数据绘制掩模图案的绘图系统。

53. 发明授权

US07523437B2 Pattern-producing method for semiconductor device 失效
标题翻译：半导体器件的图案制作方法
公开(公告)号：US07523437B2
公开(公告)日：2009-04-21
申请号：US11012492
申请日：2004-12-16
申请人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
发明人： Suigen Kyoh , Toshiya Kotani , Soichi Inoue
IPC分类号： G06F16/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.
摘要翻译：公开了一种制造用于半导体器件的图案的方法，包括提取图案布局的一部分，扰乱包含在图案布局部分中的图案以产生扰动图案，校正扰动图案，预测第一图案，为形成在晶片上，从校正的扰动图案获取扰动图案和第一图案之间的第一个差异，以及存储关于包含关于第一个差异的信息的扰动图案的信息。

54. 发明授权

US07337426B2 Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein 失效
标题翻译：图案校正方法，掩模制作方法，制造半导体器件的方法，图案校正系统以及其中记录有图案校正程序的计算机可读记录介质
公开(公告)号：US07337426B2
公开(公告)日：2008-02-26
申请号：US11115187
申请日：2005-04-27
申请人： Toshiya Kotani , Shigeki Nojima , Kazuhito Kobayashi
发明人： Toshiya Kotani , Shigeki Nojima , Kazuhito Kobayashi
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.
摘要翻译：公开了一种图案校正方法，包括提取校正图案，至少一个或多个校正图案包括在形成在基板上的第一设计图案中，从第一设计图案获取布局信息，影响成品平面形状的布局信息基于所述布局信息确定校正图案的校正内容，生成与所述布局信息对应的设计图案-2以与所述校正图案相关联，以及校正所述校正图案按照与设计模式相对应的修正内容2。

55. 发明授权

US07266801B2 Design pattern correction method and mask pattern producing method 有权
标题翻译：设计图案校正方法和掩模图案制作方法
公开(公告)号：US07266801B2
公开(公告)日：2007-09-04
申请号：US11012613
申请日：2004-12-16
申请人： Toshiya Kotani , Suigen Kyoh , Hirotaka Ichikawa
发明人： Toshiya Kotani , Suigen Kyoh , Hirotaka Ichikawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.
摘要翻译：公开了一种考虑半导体集成电路的层之间的处理余量来校正设计图案的方法，包括基于第一设计图案计算与第一层的处理图案形状相对应的第一图案形状，计算第二图案形状对应于基于第二设计图案的第二层的处理图案形状，使用第一和第二图案形状之间的布尔运算来计算第三图案形状，确定从第三图案形状获得的评估值是否满足预定的值，并且如果确定所述评估值不满足所述预定值，则校正所述第一和第二设计图案中的至少一个。

56. 发明授权

US07200833B2 Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method 失效
标题翻译：边缘偏移量的计算方法，验证方法，验证程序和验证系统以及半导体器件制造方法
公开(公告)号：US07200833B2
公开(公告)日：2007-04-03
申请号：US10801798
申请日：2004-03-17
申请人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G03F7/705
摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.
摘要翻译：将期望图案与根据设计图案预测的要在晶片上形成的光洁度图案进行比较的方法，基于光束强度的计算和完成图案与期望图案的偏差量在完成图案的每个边缘处并计算所需图案，包括设置用于在晶片上设置期望图案的参考光束强度，设置用于将完成图案与期望图案进行比较的评估点，计算光束强度在评价点，计算评价点的光束强度的微分值，计算微分值与参考光束强度的交点，计算交点与评价点之间的差，限定边缘的差完成图案与期望图案的偏差量。

57. 发明授权

US07194704B2 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US07194704B2
公开(公告)日：2007-03-20
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

58. 发明授权

US07181707B2 Method of setting process parameter and method of setting process parameter and/or design rule 有权
标题翻译：设置过程参数的方法和设置过程参数和/或设计规则的方法
公开(公告)号：US07181707B2
公开(公告)日：2007-02-20
申请号：US10385628
申请日：2003-03-12
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译：公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

59. 发明申请

US20070028205A1 Data processing method in semiconductor device, program of the same, and manufacturing method of semiconductor device 有权
标题翻译：半导体器件中的数据处理方法，程序及半导体器件的制造方法
公开(公告)号：US20070028205A1
公开(公告)日：2007-02-01
申请号：US11492802
申请日：2006-07-26
申请人： Ayako Nakano , Toshiya Kotani , Atsushi Watanabe
发明人： Ayako Nakano , Toshiya Kotani , Atsushi Watanabe
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design data processing method in a semiconductor device includes extracting, from design data, a graphic in which there exist a first wiring and a second wiring which is orthogonal to the first wiring, and changing a portion where the first wiring is orthogonal to the second wiring to make connection at an angle other than 90 degrees, thereby preparing new design data.
摘要翻译：半导体装置中的设计数据处理方法包括从设计数据提取存在与第一布线正交的第一布线和第二布线的图形，以及将第一布线正交于第二布线的部分接线以90度以外的角度进行连接，从而准备新的设计数据。

60. 发明申请

US20060197136A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060197136A1
公开(公告)日：2006-09-07
申请号：US11346293
申请日：2006-02-03
申请人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11517
摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
摘要翻译：根据本发明，实现了高可靠性的NAND型闪速存储器。它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成接线层。

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