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1. 发明授权

US07700997B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07700997B2
公开(公告)日：2010-04-20
申请号：US11346293
申请日：2006-02-03
申请人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , H01L27/11517
摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
摘要翻译：根据本发明，实现了高可靠性的NAND型闪速存储器。它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成接线层。

2. 发明申请

US20060197136A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060197136A1
公开(公告)日：2006-09-07
申请号：US11346293
申请日：2006-02-03
申请人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Takuya Futatsuyama , Toshiya Kotani , Hiromitsu Mashita , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11517
摘要： According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
摘要翻译：根据本发明，实现了高可靠性的NAND型闪速存储器。它提供一种半导体存储器件，包括：多个存储单元; 由第一栅极布线层形成的多个字线; 用于向所述字线提供电压的多个第一晶体管; 以及用于连接所述字线和所述第一晶体管的源极或漏极的电连接，所述电连接由形成在所述第一栅极布线层上方的第一布线层的第一布线和形成在所述第一晶体管上方的第二布线层的第二布线形成接线层。

3. 发明授权

US07716617B2 Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device 失效
标题翻译：半导体器件，制造图案布局的方法，制造掩模图案的方法，制作布局的方法，制造光掩模的方法，光掩模和半导体器件的制造方法
公开(公告)号：US07716617B2
公开(公告)日：2010-05-11
申请号：US11299843
申请日：2005-12-13
申请人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： G06F17/50 , H03K19/177 , H01L25/00
CPC分类号： H01L27/0207 , G03F1/00 , G03F1/36 , G06F17/5068 , H01L27/115 , H01L27/11517 , H01L27/11519
摘要： A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
摘要翻译：半导体器件包括半导体衬底和在半导体衬底上至少包括N（≥2）个电路图案的电路图案组，至少N个电路图案中的至少一个端部附近包括连接区域以电连接涉及与电路图案组不同的另一个电路图案组中的电路图案，所述至少N个布线图案包括电路图案N1和沿与电路的纵向方向不同的一个方向布置的至少一个电路图案Ni（i≥2）图案N1中，具有较大i的至少一个电路图案Ni布置在远离电路图案N1的更远位置处，并且根据包括至少Ni电路图案中的连接区域的图案，i，连接区域布置在纵向方向上的另一位置。

4. 发明申请

US20060157833A1 Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device 失效
标题翻译：半导体器件，制造图案布局的方法，制造掩模图案的方法，制作布局的方法，制造光掩模的方法，光掩模和半导体器件的制造方法
公开(公告)号：US20060157833A1
公开(公告)日：2006-07-20
申请号：US11299843
申请日：2005-12-13
申请人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L21/50 , H01L23/02
CPC分类号： H01L27/0207 , G03F1/00 , G03F1/36 , G06F17/5068 , H01L27/115 , H01L27/11517 , H01L27/11519
摘要： A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
摘要翻译：半导体器件包括半导体衬底和在半导体衬底上至少包括N（> = 2）个电路图案的电路图案组，至少N个电路图案中的至少一个端部附近包括电连接区域连接到与电路图案组不同的另一个电路图案组中的电路图案，所述至少N个配线图案包括电路图案N 1和至少一个电路图案Ni（i> = 2），该电路图案沿纵向方向电路图案N 1的至少一个电路图案Ni具有较大的i被布置在远离电路图案N 1的更远位置处，并且根据包括至少Ni电路图案中的连接区域的图案， i越大，连接区域被设置在纵向方向上的另一位置。

5. 发明申请

US20100193960A1 Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device 审中-公开
标题翻译：半导体器件，制造图案布局的方法，制造掩模图案的方法，制作布局的方法，制造光掩模的方法，光掩模和半导体器件的制造方法
公开(公告)号：US20100193960A1
公开(公告)日：2010-08-05
申请号：US12659773
申请日：2010-03-22
申请人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
发明人： Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
IPC分类号： H01L23/52 , G06F17/50 , G03F1/00
CPC分类号： H01L27/0207 , G03F1/00 , G03F1/36 , G06F17/5068 , H01L27/115 , H01L27/11517 , H01L27/11519
摘要： A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
摘要翻译：半导体器件包括半导体衬底和在半导体衬底上至少包括N（≥2）个电路图案的电路图案组，至少N个电路图案中的至少一个端部附近包括连接区域以电连接涉及与电路图案组不同的另一个电路图案组中的电路图案，所述至少N个布线图案包括电路图案N1和沿与电路的纵向方向不同的一个方向布置的至少一个电路图案Ni（i≥2）图案N1中，具有较大i的至少一个电路图案Ni布置在远离电路图案N1的更远位置处，并且根据包括至少Ni电路图案中的连接区域的图案，i，连接区域布置在纵向方向上的另一位置。

6. 发明申请

US20110047518A1 PATTERN DETERMINING METHOD 审中-公开
标题翻译：图案确定方法
公开(公告)号：US20110047518A1
公开(公告)日：2011-02-24
申请号：US12860278
申请日：2010-08-20
申请人： Issui Aiba , Takafumi Taguchi , Hiromitsu Mashita , Taiga Uno , Fumiharu Nakajima , Toshiya Kotani , Tadahito Fujisawa
发明人： Issui Aiba , Takafumi Taguchi , Hiromitsu Mashita , Taiga Uno , Fumiharu Nakajima , Toshiya Kotani , Tadahito Fujisawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： According to the embodiments, a first representative point is set on outline pattern data on a pattern formed in a process before a processed pattern. Then, a minimum distance from the first representative point to a peripheral pattern is calculated. Then, area of a region with no pattern, which is sandwiched by the first representative point and the peripheral pattern, in a region within a predetermined range from the first representative point is calculated. Then, it is determined whether the first representative point becomes a processing failure by using the minimum distance and the area.
摘要翻译：根据实施例，在处理图案之前的处理中形成的图案上的轮廓图案数据上设置第一代表点。然后，计算从第一代表点到外围图案的最小距离。然后，计算出与第一代表点和外围图案夹着的没有图案的区域的区域在距离第一代表点的预定范围内的区域中。然后，通过使用最小距离和面积确定第一代表点是否变为处理失败。

7. 发明授权

US07682757B2 Pattern layout for forming integrated circuit 有权
标题翻译：用于形成集成电路的图案布局
公开(公告)号：US07682757B2
公开(公告)日：2010-03-23
申请号：US11401837
申请日：2006-04-12
申请人： Hiromitsu Mashita , Tadahito Fujisawa , Minoru Inomoto , Koji Hashimoto , Yasunobu Kai
发明人： Hiromitsu Mashita , Tadahito Fujisawa , Minoru Inomoto , Koji Hashimoto , Yasunobu Kai
IPC分类号： G03F1/00
CPC分类号： G03F1/32 , G03F1/36
摘要： A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.
摘要翻译：用于形成集成电路的图案布局包括第一器件图案，第二器件图案和辅助图案。第一装置图案包括在第一方向上具有规则间隔的固定间距交替排列的线和空间。第二装置图案设置在固定节距上并且在第一方向上与第一装置图案分离。第二装置图案的图案宽度比固定间距的规则间隔大奇数倍，其中奇数被设定为三个以上。辅助图案设置在固定间距上并且在第二装置图案内并且被配置为不被曝光解决。

8. 发明申请

US20060228636A1 Pattern layout for forming integrated circuit 有权
标题翻译：用于形成集成电路的图案布局
公开(公告)号：US20060228636A1
公开(公告)日：2006-10-12
申请号：US11401837
申请日：2006-04-12
申请人： Hiromitsu Mashita , Tadahito Fujisawa , Minoru Inomoto , Koji Hashimoto , Yasunobu Kai
发明人： Hiromitsu Mashita , Tadahito Fujisawa , Minoru Inomoto , Koji Hashimoto , Yasunobu Kai
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/32 , G03F1/36
摘要： A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.
摘要翻译：用于形成集成电路的图案布局包括第一器件图案，第二器件图案和辅助图案。第一装置图案包括在第一方向上具有规则间隔的固定间距交替排列的线和空间。第二装置图案设置在固定节距上并且在第一方向上与第一装置图案分离。第二装置图案的图案宽度比固定间距的规则间隔大奇数倍，其中奇数被设定为三个以上。辅助图案设置在固定间距上并且在第二装置图案内并且被配置为不被曝光解决。

9. 发明授权

US07669172B2 Pattern creation method, mask manufacturing method and semiconductor device manufacturing method 失效
标题翻译：图案形成方法，掩模制造方法和半导体器件制造方法
公开(公告)号：US07669172B2
公开(公告)日：2010-02-23
申请号：US12050764
申请日：2008-03-18
申请人： Takeshi Ito , Satoshi Tanaka , Toshiya Kotani , Tadahito Fujisawa , Koji Hashimoto
发明人： Takeshi Ito , Satoshi Tanaka , Toshiya Kotani , Tadahito Fujisawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F1/00
摘要： A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.
摘要翻译：一种图案创建方法，包括在第一层上布置集成电路图案的最极端格式的数据，并且在第二层上布置不包括最末端图案的集成电路图案的数据，提取第一最接近的数据图案最接近于来自第二层的最末端图案，并将所提取的数据转换为第三层，产生在第四层中接触第一最近图案和最末端图案的接触图案的数据，产生接触图案的非重叠图案的数据，不包括在第五层中具有最末端图案和最前端图案和第一最近图案的重叠部分，提取最接近图案的第二最接近图案的数据，其最接近非重叠图案并且转换提取的数据到第一层。

10. 发明申请

US20060093926A1 Mask pattern data generating method, photo mask manufacturing method, and semiconductor device manufacturing method 失效
公开(公告)号：US20060093926A1
公开(公告)日：2006-05-04
申请号：US11259069
申请日：2005-10-27
申请人： Tadahito Fujisawa , Takeshi Ito , Toshiya Kotani
发明人： Tadahito Fujisawa , Takeshi Ito , Toshiya Kotani
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F7/70441 , G03F1/36
摘要： A mask pattern data generating method is disclosed, which comprises preparing mask pattern data which corresponds to a design pattern including a pair of line patterns formed of two line patterns, and disposing an auxiliary pattern which is un-transferable to a resist film at a center of a space region between the pair of line patterns, in which the disposing of the auxiliary pattern includes obtaining a shape of the auxiliary pattern which meets formulae in which a width in the short edge direction of the auxiliary pattern, a space width between the auxiliary pattern and one of the pair of line patterns, a wavelength of an exposure light emitted by a projection aligner using a photo mask at exposure, and a numerical apertures of a projection lens of the projection aligner are defined as parameters, and disposing the obtained auxiliary pattern at the center of the space region.

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