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    • 51. 发明授权
    • Programmable memory devices with latching buffer circuit and methods for operating the same
    • 具有锁存缓冲电路的可编程存储器件及其操作方法
    • US06826082B2
    • 2004-11-30
    • US10403739
    • 2003-03-31
    • Sang-Won HwangSung-Soo Lee
    • Sang-Won HwangSung-Soo Lee
    • G11C1604
    • G11C16/3459G11C7/065G11C16/24
    • Programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between the bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node. Methods of operating the same are also provided.
    • 可编程存储器件包括具有相关位线的存储单元。 缓冲电路将位线耦合到数据线。 缓冲电路具有耦合到位线的感测节点,并且包括具有耦合到数据线的锁存节点的锁存电路。 控制电路在存储器单元的编程操作与其对应的程序验证操作之间复位锁存节点。 存储器件可以是NAND型闪存器件,并且存储器单元可以是在位线和公共源极线之间串联连接的一串存储器单元之一。 晶体管可以将数据线耦合到锁存节点,并且晶体管可以将锁存器节点耦合到感测节点。 还提供了其操作方法。
    • 56. 发明授权
    • Method and circuit for repairing defect in a semiconductor memory device
    • 修复半导体存储器件缺陷的方法和电路
    • US5548555A
    • 1996-08-20
    • US420835
    • 1995-04-11
    • Sung-Soo LeeJin-Ki Kim
    • Sung-Soo LeeJin-Ki Kim
    • G11C29/00G11C29/04G11C29/24G11C7/00
    • G11C29/785G11C29/24
    • A method and a circuit for repairing defect by substituting a redundant memory cell for a defective memory cell in the semiconductor memory device. The circuit comprises charging nodes connected parallel to a number of electrical fuses; a device for outputting a storage signal of a defective address in response to an external control signal; a device for providing current to the charging node in response to the storage signal of the defective address; a redundant sense amplifier for outputting a redundant block driving signal to substitute a defective address in response to a logic level of the charging node; and a controller for decoding an address signal provided from the outside of the memory device so that a current path is formed in a selected fuse and the fuse is blew by current provided from the charging node, the controller being activated by the storage signal of the defective address.
    • 一种用于通过在半导体存储器件中替换有缺陷存储单元的冗余存储单元来修复缺陷的方法和电路。 该电路包括与多个电保险丝并联连接的充电节点; 用于响应于外部控制信号输出缺陷地址的存储信号的装置; 用于响应于所述有缺陷地址的存储信号向所述计费节点提供电流的装置; 冗余感测放大器,用于响应于所述充电节点的逻辑电平输出冗余块驱动信号以代替缺陷地址; 以及控制器,用于对从存储器件的外部提供的地址信号进行解码,使得电流路径形成在所选择的熔丝中,并且熔丝被从充电节点提供的电流吹动,所述控制器由所述存储信号的存储信号激活 有缺陷的地址。
    • 59. 发明申请
    • METHOD OF TESTING AN OBJECT AND APPARATUS FOR PERFORMING THE SAME
    • 测试对象的方法和执行该对象的设备
    • US20120150478A1
    • 2012-06-14
    • US13325154
    • 2011-12-14
    • Ki-Jae SongSung-Soo Lee
    • Ki-Jae SongSung-Soo Lee
    • G06F19/00H01L21/66G01R31/26
    • G01R31/31908G01R31/318513G01R31/31919
    • In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.
    • 在测试对象的方法中,可以在测试器中设置用于测试对象中的第一设备的第一测试模式。 用于测试物体中的第二装置的第二测试图案可以设置在电连接在测试器和物体之间的测试头中。 可以通过测试头将第一测试图案提供给第一设备,并且可以由测试头将第二测试图案提供给第二设备,以同时测试第一设备和第二设备。 因此,可以在不改变测试器中的测试条件的情况下同时测试彼此不同的第一设备和第二设备,从而可以减少测试对象的时间。