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51. 发明授权

US08560795B2 Memory arrangement for multi-processor systems including a memory queue 有权
标题翻译：包括内存队列在内的多处理器系统的内存布置
公开(公告)号：US08560795B2
公开(公告)日：2013-10-15
申请号：US11966832
申请日：2007-12-28
申请人： Bingfeng Mei , Suk Jin Kim , Osman Allam
发明人： Bingfeng Mei , Suk Jin Kim , Osman Allam
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F13/1642
摘要： A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).
摘要翻译：公开了适用于多处理器系统或阵列的硬件存储器架构或布置。在一个方面，存储器装置包括功能单元（例如，计算单元）和功能单元访问（用于写入和/或读取访问）的至少一个存储器件之间的至少一个存储器队列。

52. 发明授权

US08433829B2 Direct memory access controller and method of operating the same 有权
标题翻译：直接内存访问控制器和操作方法相同
公开(公告)号：US08433829B2
公开(公告)日：2013-04-30
申请号：US12948516
申请日：2010-11-17
申请人： Ki-Seok Kwon , Jae-Un Park , Suk-Jin Kim
发明人： Ki-Seok Kwon , Jae-Un Park , Suk-Jin Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G11C15/00
摘要： Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.
摘要翻译：提供了一种直接存储器访问（DMA）控制器，其提供了在DMA传输期间正在传输的数据中搜索特定模式的功能。 DMA控制器存储至少一个模式值。 DMA控制器在使用DMA方法发送数据的同时将正在发送的数据与模式值进行比较，并且响应于正被检测的图案值的数据匹配而产生指示已经检测到与模式值匹配的数据的信号。 DMA控制器响应于所生成的信号存储与模式值匹配的数据的地址。

53. 发明授权

US08214617B2 Apparatus and method of avoiding bank conflict in single-port multi-bank memory system 有权
标题翻译：避免单端口多库存储系统存在冲突的装置和方法
公开(公告)号：US08214617B2
公开(公告)日：2012-07-03
申请号：US12071910
申请日：2008-02-27
申请人： Kyoung-june Min , Chan-min Park , Suk-jin Kim , Won-jong Lee , Kwon-taek Kwon , Hee-seok Kim
发明人： Kyoung-june Min , Chan-min Park , Suk-jin Kim , Won-jong Lee , Kwon-taek Kwon , Hee-seok Kim
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836
摘要： Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.
摘要翻译：提供了一种避免银行冲突的方法和装置。通过将第一指令的执行定时改变为在第一指令的执行定时之前的定时，以访问指令来替换作为预测导致存储体冲突的访问指令之一的第一指令，不造成银行冲突。接下来，根据第一指令被调度为访问存储体的加载/存储单元访问存储体，并在第二指令的执行定时从存储体读出数据，然后允许加载/存储单元在第一指令的执行定时输入读数据。因此，尽管预测导致银行冲突的访问指令被分配给加载/存储单元，但是可以防止银行冲突，使得可以避免由于银行冲突的发生导致的性能下降。

54. 发明申请

US20120124116A1 APPARATUS AND METHOD FOR CONVERTING DATA BETWEEN A FLOATING-POINT NUMBER AND AN INTEGER 有权
标题翻译：用于转换浮点数和整数之间的数据的装置和方法
公开(公告)号：US20120124116A1
公开(公告)日：2012-05-17
申请号：US13101356
申请日：2011-05-05
申请人： Hyeong-Seok YU , Suk-Jin Kim , Sang-Su Park , Yong-Surk Lee
发明人： Hyeong-Seok YU , Suk-Jin Kim , Sang-Su Park , Yong-Surk Lee
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , H03M7/24
摘要： An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.
摘要翻译：提供了一种用于在浮点数和整数之间转换数据的装置和方法。该装置包括：数据转换器，被配置为基于输入二进制数据的符号和输出格式确定输入二进制数据的符号和输出格式，转换输入的二进制数据并将输入的二进制数据转换为补码数据，偏置值发生器，被配置为基于所输入的二进制数据的舍入模式来确定输入的二进制数据是否被舍入，并相应地生成偏差值; 以及加法器，被配置为通过将所述补码和偏置值相加来将输入的二进制数据转换成二进制补码。

55. 发明申请

US20110138086A1 DIRECT MEMORY ACCESS CONTROLLER AND METHOD OF OPERATING THE SAME 有权
标题翻译：直接存储器访问控制器及其操作方法
公开(公告)号：US20110138086A1
公开(公告)日：2011-06-09
申请号：US12948516
申请日：2010-11-17
申请人： Ki-Seok KWON , Jae-Un Park , Suk-Jin Kim
发明人： Ki-Seok KWON , Jae-Un Park , Suk-Jin Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G11C15/00
摘要： Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.
摘要翻译：提供了一种直接存储器访问（DMA）控制器，其提供了在DMA传输期间正在传输的数据中搜索特定模式的功能。 DMA控制器存储至少一个模式值。 DMA控制器在使用DMA方法发送数据的同时将正在发送的数据与模式值进行比较，并且响应于正被检测的图案值的数据匹配而产生指示已经检测到与模式值匹配的数据的信号。 DMA控制器响应于所生成的信号存储与模式值匹配的数据的地址。

56. 发明授权

US07562107B2 Mixed-type adder comprising multiple sub-adders having different carry propagation schemes 失效
标题翻译：混合型加法器包括具有不同进位传播方案的多个子加法器
公开(公告)号：US07562107B2
公开(公告)日：2009-07-14
申请号：US11134615
申请日：2005-05-19
申请人： Jeong-A Lee , Ki-Seon Kim , Jeong-Gun Lee , Suk-Jin Kim
发明人： Jeong-A Lee , Ki-Seon Kim , Jeong-Gun Lee , Suk-Jin Kim
IPC分类号： G06F7/50
CPC分类号： G06F7/506 , G06F7/507 , G06F7/508
摘要： Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder is divided into I bit groups which are respectively allocated to the I sub adders. The I sub adders have different carry propagation schemes and are connected in series through a carry signal.
摘要翻译：公开了一种具有优化设计成本的混合型加法器。混合型加法器包括I子加法器（其中，I为大于1的正数）。混合型加法器的总位宽度分为分配给I子加法器的I比特组。 I子加法器具有不同的进位传播方案，并通过进位信号串联连接。

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