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1. 发明授权

US08560795B2 Memory arrangement for multi-processor systems including a memory queue 有权
标题翻译：包括内存队列在内的多处理器系统的内存布置
公开(公告)号：US08560795B2
公开(公告)日：2013-10-15
申请号：US11966832
申请日：2007-12-28
申请人： Bingfeng Mei , Suk Jin Kim , Osman Allam
发明人： Bingfeng Mei , Suk Jin Kim , Osman Allam
IPC分类号： G06F12/00
CPC分类号： G06F12/0851 , G06F13/1642
摘要： A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).
摘要翻译：公开了适用于多处理器系统或阵列的硬件存储器架构或布置。在一个方面，存储器装置包括功能单元（例如，计算单元）和功能单元访问（用于写入和/或读取访问）的至少一个存储器件之间的至少一个存储器队列。

2. 发明申请

US20080140980A1 MEMORY ARRANGEMENT FOR MULTI-PROCESSOR SYSTEMS 有权
标题翻译：多处理器系统的内存安排
公开(公告)号：US20080140980A1
公开(公告)日：2008-06-12
申请号：US11966832
申请日：2007-12-28
申请人： Bingfeng Mei , Suk Jin Kim , Osman Allam
发明人： Bingfeng Mei , Suk Jin Kim , Osman Allam
IPC分类号： G06F12/02 , G06F9/38
CPC分类号： G06F12/0851 , G06F13/1642
摘要： A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).
摘要翻译：公开了适用于多处理器系统或阵列的硬件存储器架构或布置。在一个方面，存储器装置包括功能单元（例如，计算单元）和功能单元访问（用于写入和/或读取访问）的至少一个存储器件之间的至少一个存储器队列。

3. 发明授权

US08443174B2 Processor and method of performing speculative load operations of the processor 有权
标题翻译：处理器和执行处理器的推测加载操作的方法
公开(公告)号：US08443174B2
公开(公告)日：2013-05-14
申请号：US11838488
申请日：2007-08-14
申请人： Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Suk Jin Kim
发明人： Hong-Seok Kim , Hee Seok Kim , Jeongwook Kim , Suk Jin Kim
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3842
摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.
摘要翻译：提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用一种类似软件的方法，从而提高处理器的性能。

4. 发明申请

US20080068375A1 Method and system for early Z test in title-based three-dimensional rendering 审中-公开
标题翻译：基于标题的三维渲染的早期Z检验方法与系统
公开(公告)号：US20080068375A1
公开(公告)日：2008-03-20
申请号：US11655244
申请日：2007-01-19
申请人： Kyoung June Min , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
发明人： Kyoung June Min , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.
摘要翻译：提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

5. 发明授权

US06425273B1 Tubular lever lock 失效
标题翻译：管状杆锁
公开(公告)号：US06425273B1
公开(公告)日：2002-07-30
申请号：US09466695
申请日：1999-12-20
申请人： Dae Young Kim , Suk Jin Kim
发明人： Dae Young Kim , Suk Jin Kim
IPC分类号： B60R2502
CPC分类号： E05B55/005 , E05B13/002 , E05B13/108 , Y10T70/5416 , Y10T70/5496 , Y10T70/5832 , Y10T292/57 , Y10T292/93
摘要： A tubular lever lock includes a protruded connection part formed at the cross section of a pawl which slides along an inner spindle and interfaced with the operation of an eccentric hole of an operation globe. The spindles are structured to form and to protrude with a square pole passing through a latch by an appropriate distance. A key holder is formed on an outer bundle and is connected with a lock cylinder of an outer spindle, which enables a catch hub installed inwardly and elastically to rotate. With regard to the inner bundle and outer bundle, when built in, the key holder of the outer bundle causes connection with the operation globe through a square hole of a catch hub as well as a hole of the square pole.
摘要翻译：管状杠杆锁包括形成在棘爪的横截面上的突出连接部分，其沿着内主轴滑动并与操作球体的偏心孔的操作接合。主轴构造成形成并突出有方形的杆穿过闩锁适当的距离。钥匙保持器形成在外束上并且与外心轴的锁芯连接，这使得能够向内并弹性地旋转的止动轮毂。对于内束和外束，当内置钥匙架时，外束的钥匙架通过捕获轮毂的方孔以及方杆的孔与操作球体连接。

6. 发明授权

US08345064B2 Method and system for tile binning using half-plane edge function 有权
标题翻译：使用半平面边缘函数的瓦片合并的方法和系统
公开(公告)号：US08345064B2
公开(公告)日：2013-01-01
申请号：US11604691
申请日：2006-11-28
申请人： Kyoung June Min , Jeong Wook Kim , Dong Soo Kang , Suk Jin Kim , Hee Seok Kim , Seok Yoon Jung , Sang Oak Woo
发明人： Kyoung June Min , Jeong Wook Kim , Dong Soo Kang , Suk Jin Kim , Hee Seok Kim , Seok Yoon Jung , Sang Oak Woo
IPC分类号： G09G5/00
CPC分类号： G06T15/00
摘要： A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.
摘要翻译：一种瓦片合并方法，包括：将用于渲染三角形的场景划分成多个瓦片; 确定每个瓦片的瓦片节点的识别值; 以及基于每个瓦片的瓦片节点的标识值，从瓦片识别包括三角形的整体或部分的瓦片。

7. 发明申请

US20110193862A1 METHOD AND SYSTEM FOR EARLY Z TEST IN TITLE-BASED THREE-DIMENSIONAL RENDERING 有权
标题翻译：用于基于三维三维渲染的早期Z测试的方法和系统
公开(公告)号：US20110193862A1
公开(公告)日：2011-08-11
申请号：US13090924
申请日：2011-04-20
申请人： Kyoung June MIN , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
发明人： Kyoung June MIN , Jong Myon Kim , Hee Seok Kim , Jeong Wook Kim , Suk Jin Kim
IPC分类号： G06T15/00
CPC分类号： G06T15/405
摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.
摘要翻译：提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。

8. 发明授权

US07478227B2 Apparatus and method for optimizing loop buffer in reconfigurable processor 有权
标题翻译：用于优化可重构处理器中循环缓冲器的装置和方法
公开(公告)号：US07478227B2
公开(公告)日：2009-01-13
申请号：US11525913
申请日：2006-09-25
申请人： Soo Jung Ryu , Jeong Wook Kim , Suk Jin Kim , Hong-Seok Kim
发明人： Soo Jung Ryu , Jeong Wook Kim , Suk Jin Kim , Hong-Seok Kim
IPC分类号： G06F9/40
CPC分类号： G06F17/5054 , G06F9/381 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.
摘要翻译：一种可重配置处理器，包括用于存储用于至少一个环路配置的配置位的配置存储器; 用于存储指示循环中的操作是否为延迟操作的位信息的有效信息存储器; 以及至少一个处理单元，用于通过参考从有效信息存储器发送的比特信息来确定下一个周期中的操作是否是延迟操作，并且根据来自所述有用信息存储器的配置位选择性地执行改变和配置的实现基于确定结果的配置存储器。

9. 发明授权

US08943503B2 Apparatus and method for thread progress tracking using deterministic progress index 有权
标题翻译：使用确定性进度指标进行线程进度跟踪的装置和方法
公开(公告)号：US08943503B2
公开(公告)日：2015-01-27
申请号：US13156492
申请日：2011-06-09
申请人： Young Sam Shin , Seung Won Lee , Shi Hwa Lee , Suk Jin Kim , Min Young Son
发明人： Young Sam Shin , Seung Won Lee , Shi Hwa Lee , Suk Jin Kim , Min Young Son
IPC分类号： G06F9/46 , G06F11/34
CPC分类号： G06F11/3466 , G06F11/3423 , G06F2201/88
摘要： Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.
摘要翻译：提供了一种用于测量应用程序的性能或进展状态以便在使用微架构的计算环境中执行数据处理并执行特定功能的方法和装置。线程进度跟踪装置可以包括：选择器，用于选择构成应用程序的至少一个线程; 确定单元，基于预定标准，确定指令执行方案是否对应于具有规则周期的确定性执行方案或具有相对于构成对应线程的至少一个指令中的每一个指令具有不规则延迟周期的非确定性执行方案 ; 以及确定性进度计数器，用于生成关于由确定性执行方案执行的指令的确定性进度索引，不包括由非确定性执行方案执行的指令。

10. 发明授权

US08495303B2 Processor and computer system with buffer memory 有权
标题翻译：具有缓冲存储器的处理器和计算机系统
公开(公告)号：US08495303B2
公开(公告)日：2013-07-23
申请号：US12176605
申请日：2008-07-21
申请人： Sang Suk Lee , Suk Jin Kim , Yeon Gon Cho
发明人： Sang Suk Lee , Suk Jin Kim , Yeon Gon Cho
IPC分类号： G06F13/00
CPC分类号： G06F12/0846 , G06F9/3824
摘要： A processor and a computing system include a processor core and a buffer memory to read word data from a memory. The read word data includes first byte data read by the processor core from the memory. The buffer memory also stores the read word data, and determines whether second byte data requested by the processor core is stored in the buffer memory.
摘要翻译：处理器和计算系统包括处理器核心和用于从存储器读取字数据的缓冲存储器。读字数据包括处理器核从存储器读取的第一字节数据。缓冲存储器还存储读字数据，并且确定处理器核请求的第二字节数据是否被存储在缓冲存储器中。

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