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51. 发明授权

US07453878B1 System and method for ordering of data transferred over multiple channels 有权
标题翻译：用于对通过多个通道传输的数据进行排序的系统和方法
公开(公告)号：US07453878B1
公开(公告)日：2008-11-18
申请号：US09910587
申请日：2001-07-20
申请人： Randal G. Martin , Steven C. Miller , Mark D. Stadler , David A. Kruckemyer
发明人： Randal G. Martin , Steven C. Miller , Mark D. Stadler , David A. Kruckemyer
IPC分类号： H04L12/56 , H04L12/26 , H04J3/16
CPC分类号： H04L47/34 , H04L45/24 , H04L47/10 , H04L47/26 , H04L47/266 , H04L47/39 , H04L47/41
摘要： A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).
摘要翻译：多通道数据传输系统（10）包括一个源（12），其生成具有用于在多个请求信道（14）上传送的序列号的数据分组。数据分组通过多个请求信道（14）通过网络（16）传送到目的地（18）。目的地（18）响应于序列号，将通过多个请求信道（14）接收的数据分组重新排序成适当的序列，以便于数据处理。目的地（18）通过多个响应信道（20）向源（12）提供适当的应答分组，以控制来自源（12）的数据分组的流。

52. 发明授权

US06981101B1 Method and system for maintaining data at input/output (I/O) interfaces for a multiprocessor system 有权
标题翻译：用于在多处理器系统的输入/输出（I / O）接口上维护数据的方法和系统
公开(公告)号：US06981101B1
公开(公告)日：2005-12-27
申请号：US09910531
申请日：2001-07-20
申请人： Steven C. Miller , Daniel E. Lenoski , Kevin Knecht , George Hopkins , Michael S. Woodacre
发明人： Steven C. Miller , Daniel E. Lenoski , Kevin Knecht , George Hopkins , Michael S. Woodacre
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0817 , G06F12/0808 , G06F12/0813 , G06F12/0862 , G06F2212/2542 , G06F2212/621
摘要： A multiprocessor system and method includes a processing sub-system having a plurality of processors and a processor memory system. A scalable network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces. Each I/O interface has a local cache and is operable to couple a peripheral device to the multiprocessor system and to store copies of data from the processor memory system in the local cache for use by the peripheral device. A coherence domain for the multiprocessor system includes the processors and processor memory system of the processing sub-system and the local caches of the I/O sub-system.
摘要翻译：多处理器系统和方法包括具有多个处理器和处理器存储器系统的处理子系统。可扩展网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口。每个I / O接口具有本地高速缓存，并且可操作以将外围设备耦合到多处理器系统，并将来自处理器存储器系统的数据副本存储在本地高速缓存中供外围设备使用。多处理器系统的相干域包括处理子系统的处理器和处理器存储器系统以及I / O子系统的本地高速缓存。

53. 发明授权

US08402225B2 Method for performing cache coherency in a computer system 失效
标题翻译：在计算机系统中执行高速缓存一致性的方法
公开(公告)号：US08402225B2
公开(公告)日：2013-03-19
申请号：US12887374
申请日：2010-09-21
申请人： Steven C. Miller , Martin M. Deneroff , Kenneth C. Yeager
发明人： Steven C. Miller , Martin M. Deneroff , Kenneth C. Yeager
IPC分类号： G06F13/20
CPC分类号： G06F12/0815 , G06F12/0808
摘要： In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.
摘要翻译：在计算系统中，通过选择用于第一存储器事务的多个一致性协议之一来执行高速缓存一致性。多个一致性协议中的每一个具有可以应用于第一存储器事务的缓存数据的唯一的高速缓存状态集合。通过应用多个相关协议中所选择的一个的一组缓存状态，在计算系统中的适当的高速缓存上执行高速缓存一致性。

54. 发明申请

US20110191545A1 SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN A COMPUTING SYSTEM 有权
标题翻译：用于在计算机系统中执行存储器操作的系统和方法
公开(公告)号：US20110191545A1
公开(公告)日：2011-08-04
申请号：US13084280
申请日：2011-04-11
申请人： Steven C. Miller , Martin M. Deneroff , Curt F. Schimmel , Larry Rudolph , Charles E. Leiserson , Bradley C. Kuszmaul , Krste Asanovic
发明人： Steven C. Miller , Martin M. Deneroff , Curt F. Schimmel , Larry Rudolph , Charles E. Leiserson , Bradley C. Kuszmaul , Krste Asanovic
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F12/0831
摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
摘要翻译：处理器可以以多个操作状态中的一个操作。在正常操作状态下，处理器不涉及存储器事务。在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。更改变为可见后，处理器返回到正常运行状态。如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

55. 发明申请

US20110035548A1 HYBRID MEDIA STORAGE SYSTEM ARCHITECTURE 有权
标题翻译：混合媒体存储系统架构
公开(公告)号：US20110035548A1
公开(公告)日：2011-02-10
申请号：US12517473
申请日：2009-02-11
申请人： Jeffrey S. Kimmel , Steven R. Kleiman , Steven C. Miller
发明人： Jeffrey S. Kimmel , Steven R. Kleiman , Steven C. Miller
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F3/0647 , G06F3/061 , G06F3/0616 , G06F3/0643 , G06F3/0685 , G06F11/108 , G06F17/30185 , G06F17/30218 , G06F2211/109
摘要： A hybrid media storage architecture has a log-structured file system configured to control a plurality of different storage media organized as hybrid storage media that cooperate to provide a total storage space of a storage system. The log-structured file system is configured to perform initial placement and migration of data, as well as fine-grain write allocation of the data, among storage space locations of the hybrid storage media to thereby improve the performance characteristics of the media. By defining and implementing heuristics and policies directed to, e.g., types of data, the file system may initially place data on any of the different media and thereafter migrate data between the media at fine granularity and without the need for manual enforcement.
摘要翻译：混合媒体存储架构具有日志结构化文件系统，其被配置为控制组织为混合存储介质的多个不同的存储介质，所述混合存储介质协作以提供存储系统的总存储空间。日志结构文件系统被配置为在混合存储介质的存储空间位置之间执行数据的初始放置和迁移以及数据的细粒度写入分配，从而提高媒体的性能特性。通过定义和实现针对例如数据类型的启发式和策略，文件系统可以最初将数据放置在任何不同的介质上，然后以细粒度在介质之间迁移数据，而不需要手动执行。

56. 发明申请

US20110016277A1 Method for Performing Cache Coherency in a Computer System 失效
标题翻译：在计算机系统中执行缓存一致性的方法
公开(公告)号：US20110016277A1
公开(公告)日：2011-01-20
申请号：US12887374
申请日：2010-09-21
申请人： Steven C. Miller , Martin M. Deneroff , Kenneth C. Yeager
发明人： Steven C. Miller , Martin M. Deneroff , Kenneth C. Yeager
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F12/0808
摘要： In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.
摘要翻译：在计算系统中，通过选择用于第一存储器事务的多个一致性协议之一来执行高速缓存一致性。多个一致性协议中的每一个具有可以应用于第一存储器事务的缓存数据的唯一的高速缓存状态集合。通过应用多个相关协议中所选择的一个的一组缓存状态，在计算系统中的适当的高速缓存上执行高速缓存一致性。

57. 发明授权

US07873741B2 System and method for conveying information 有权
标题翻译：用于传达信息的系统和方法
公开(公告)号：US07873741B2
公开(公告)日：2011-01-18
申请号：US12264871
申请日：2008-11-04
申请人： Steven C. Miller , Thomas Edward McGee , Bruce Alan Strangfeld
发明人： Steven C. Miller , Thomas Edward McGee , Bruce Alan Strangfeld
IPC分类号： G06F15/16
CPC分类号： H03M13/05 , G06F13/4217 , G06F15/16
摘要： A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.
摘要翻译：用于传送数据的系统和方法包括确定在计算机模块处是否已经接收到交易请求信用的能力，指示可以发送交易请求消息的至少一部分的交易请求信用。系统和方法还包括确定是否要发送交易请求消息的能力，是否可以发送交易请求消息的至少一部分，并且如果可以发送交易请求消息的至少一部分被发送。

58. 发明授权

US07806827B2 Ultrasound breast screening device 有权
标题翻译：超声乳房筛查装置
公开(公告)号：US07806827B2
公开(公告)日：2010-10-05
申请号：US10616319
申请日：2003-07-09
申请人： Heidi D. Zhang , Robert F. Lawrence , Gilbert M. Lima , Steven C. Miller , Anne L. Hall
发明人： Heidi D. Zhang , Robert F. Lawrence , Gilbert M. Lima , Steven C. Miller , Anne L. Hall
IPC分类号： A61B8/00
CPC分类号： A61B8/4218 , A61B6/502 , A61B8/0825 , A61B8/42 , A61B8/4416 , G01S7/52079 , G01S15/8915 , G01S15/8938 , G01S15/899
摘要： An ultrasound breast imaging assembly includes first and second compression plates angled with respect to one another, a breast compression area defined between the first and second compression plates, at least one pivot assembly, and an ultrasound probe. The pivot assembly allows relative motion between the first and second compression plates. The ultrasound probe, which is configured to translate over one of the first and second compression plates, includes an active matrix array (AMA) positioned on one of the first and second compression plates.
摘要翻译：超声乳房成像组件包括相对于彼此成角度的第一和第二压缩板，限定在第一和第二压缩板之间的乳房压缩区域，至少一个枢轴组件和超声波探头。枢轴组件允许第一和第二压缩板之间的相对运动。配置成平移第一和第二压缩板中的一个的超声波探头包括位于第一和第二压缩板之一上的有源矩阵阵列（AMA）。

59. 发明授权

US07674588B2 Screening using polarization anisotropy in FRET emissions 失效
标题翻译：在FRET排放中使用偏振各向异性进行筛选
公开(公告)号：US07674588B2
公开(公告)日：2010-03-09
申请号：US12069724
申请日：2008-02-11
申请人： Steven C. Miller , Paul B. Comita , Christopher B. Shumate , Evan F. Cromwell
发明人： Steven C. Miller , Paul B. Comita , Christopher B. Shumate , Evan F. Cromwell
IPC分类号： C12Q1/68 , G01N33/53 , C07H21/02 , C07H21/04
CPC分类号： G01N33/542 , G01N2500/00
摘要： Methods and apparatus are described for detecting specific binding between first and second chemical entities. The first chemical entity in association with a first fluorophore is immobilized. The second chemical entity is allowed to bind with the immobilized first chemical entity. The second chemical entity is or becomes coupled to a second fluorophore, which forms a FRET pair with the first fluorophore. The bound chemical entities are exposed to radiation at an excitation frequency for either the first or the second fluorophore, and polarization anisotropy of a FRET fluorescent signal from the bound chemical entities is measured to detect specific binding between the first and second chemical entities. Techniques are also disclosed for detecting whether a FRET interaction is occurring between a first chemical entity including a donor fluorophore and a second chemical entity including an acceptor fluorophore, using simultaneous anisotropy measurements at the wavelengths of the donor and acceptor fluorophores.
摘要翻译：描述了用于检测第一和第二化学实体之间的特异性结合的方法和装置。与第一荧光团相关联的第一化学实体被固定化。允许第二化学实体与固定化的第一化学实体结合。第二化学实体是或连接到与第一荧光团形成FRET对的第二荧光团。结合的化学实体以第一或第二荧光团的激发频率暴露于辐射，并且测量来自结合的化学实体的FRET荧光信号的偏振各向异性以检测第一和第二化学实体之间的特异性结合。还公开了用于检测在包括供体荧光团的第一化学实体和包括受体荧光团的第二化学实体之间是否发生FRET相互作用的技术，其使用在供体和受体荧光团的波长处的同时各向异性测量。

60. 发明授权

US07197589B1 System and method for providing access to a bus 有权
标题翻译：提供对总线访问的系统和方法
公开(公告)号：US07197589B1
公开(公告)日：2007-03-27
申请号：US09315806
申请日：1999-05-21
申请人： Martin M. Deneroff , Steven C. Miller
发明人： Martin M. Deneroff , Steven C. Miller
IPC分类号： G06F13/00 , G06F13/36
CPC分类号： G06F13/4068 , G06F13/364
摘要： A computer system (10) includes a bus controller (12), a bus (14), a plurality of processing devices (16) and a plurality of enabling switches (18). Each enabling switch (18) corresponds to a separate one of the processing devices (16). Each processing device (16) sends an access request (24) to arbitration logic (22) in the bus controller (12), requesting access to the bus (14). The arbitration logic (22) selects one of the access requests (24) according to a priority protocol. The arbitration logic (22) generates a control signal (20) associated with the selected access request (24). The control signal (20) is provided to the enabling switch (18) corresponding to the processing device (16) that sent the selected access request (24). The enabling switch (18) enables access to the bus (14) for the processing device (16) in response to the control signal (20). In this manner, the computer system (10) can limit a number of processing devices (16) having access to the bus (14) in order to control a load on the bus (14).
摘要翻译：计算机系统（10）包括总线控制器（12），总线（14），多个处理设备（16）和多个使能开关（18）。每个使能开关（18）对应于处理设备（16）中的单独的一个。每个处理设备（16）向总线控制器（12）中的仲裁逻辑（22）发送访问请求（24），请求访问总线（14）。仲裁逻辑（22）根据优先级协议选择访问请求（24）之一。仲裁逻辑（22）产生与所选择的访问请求（24）相关联的控制信号（20）。控制信号（20）被提供给与发送所选择的访问请求（24）的处理设备（16）相对应的使能开关（18）。使能开关（18）能够响应于控制信号（20）访问处理设备（16）的总线（14）。以这种方式，计算机系统（10）可以限制具有访问总线（14）的多个处理设备（16），以便控制总线（14）上的负载。

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