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51. 发明申请

US20090242962A1 Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices 有权
标题翻译：存储层的等离子体氧化在非挥发性电荷陷阱存储器件中形成阻挡层
公开(公告)号：US20090242962A1
公开(公告)日：2009-10-01
申请号：US12080175
申请日：2008-03-31
申请人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
发明人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
IPC分类号： H01L21/28 , H01L29/423
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H2) and oxygen (O2) gas mixture into a process chamber and exposing the substrate to a plasma. In a preferred embodiment, a high density plasma (HDP) chamber is employed to oxidize a portion of the charge trapping layer. In further embodiments, a portion of a silicon-rich silicon oxynitride charge trapping layer is consumptively oxidized to form the blocking layer and provide an increased memory window relative to oxidation of a nitrogen-rich silicon oxynitride layer.
摘要翻译：通过氧化存储器件的电荷俘获层的一部分来形成非易失性电荷陷阱存储器件的阻挡层。在一个实施方案中，通过自由基氧化法在低于500℃的温度下生长阻挡层。根据一个实施方案，自由基氧化过程包括将氢（H 2）和氧（O 2）气体混合物流入处理室并暴露衬底到等离子体。在优选实施例中，使用高密度等离子体（HDP）室来氧化电荷俘获层的一部分。在另外的实施例中，一部分富硅氧氮化硅电荷捕获层被消耗氧化以形成阻挡层，并且相对于富氮氧氮化硅层的氧化提供增加的存储窗口。

52. 发明申请

US20090179253A1 Oxide-nitride-oxide stack having multiple oxynitride layers 审中-公开
标题翻译：具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠
公开(公告)号：US20090179253A1
公开(公告)日：2009-07-16
申请号：US11811958
申请日：2007-06-13
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/0214 , C23C16/0272 , C23C16/308 , G11C16/0466 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/3145 , H01L27/11568 , H01L29/40117 , H01L29/518 , H01L29/7833 , H01L29/792
摘要： A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.
摘要翻译：提供了包括具有多层电荷存储层的氧化物 - 氧化物 - 氧化物（ONO）结构的半导体器件及其形成方法。通常，该方法包括：（i）形成ONO结构的第一氧化物层; （ii）在所述第一氧化物层的表面上形成包含氮化物的多层电荷存储层; 和（iii）在多层电荷存储层的表面上形成ONO结构的第二氧化物层。优选地，电荷存储层包括至少两个氧氮，氮和/或硅具有不同化学计量组成的氮氧化硅层。更优选地，ONO结构是氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）结构的一部分，并且半导体器件是SONOS存储晶体管。还公开了其他实施例。

53. 发明申请

US20080296664A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 有权
公开(公告)号：US20080296664A1
公开(公告)日：2008-12-04
申请号：US12185751
申请日：2008-08-04
申请人： Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy
发明人： Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

54. 发明申请

US20080293254A1 Single-wafer process for fabricating a nonvolatile charge trap memory device 有权
标题翻译：用于制造非易失性电荷陷阱存储器件的单晶片工艺
公开(公告)号：US20080293254A1
公开(公告)日：2008-11-27
申请号：US11904513
申请日：2007-09-26
申请人： Krishnaswamy Ramkumar , Sagy Levy
发明人： Krishnaswamy Ramkumar , Sagy Levy
IPC分类号： H01L21/314
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833 , Y10S438/954
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。

55. 发明申请

US20080293207A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 有权
标题翻译：非挥发性电荷捕获存储器件和逻辑CMOS器件的集成
公开(公告)号：US20080293207A1
公开(公告)日：2008-11-27
申请号：US12125864
申请日：2008-05-22
申请人： William W.C. Koutny, JR. , Sam Geha , Igor Kouznetsov , Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy , Ravindra Kapre , Jeremy Warren
发明人： William W.C. Koutny, JR. , Sam Geha , Igor Kouznetsov , Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy , Ravindra Kapre , Jeremy Warren
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

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