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51. 发明申请

US20070247186A1 SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM 失效
标题翻译：具有功率降低机制的半导体集成电路
公开(公告)号：US20070247186A1
公开(公告)日：2007-10-25
申请号：US11768981
申请日：2007-06-27
申请人： Takeshi SAKATA , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi SAKATA , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K17/16
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements. In addition, current which is allowed to flow by the another one of the first switching elements is sufficient to permit the circuit block relating to another one of the first switching elements to logically operate.
摘要翻译：具有绝对值的工作电压的半导体集成电路为2.5V以下，包括由第一和第二电力线提供工作电压的电路块和每个电路块的第一开关元件。每个电路块包括即使在栅极电压等于源极电压的条件下漏电流也流过的第一MOS晶体管。每个第一开关元件控制流过每个电路块的对应的第一MOS晶体管的漏电流。此外，虽然控制第一开关元件中的一个以减少流过与第一开关元件之一相关的电路块的漏电流，但是第一开关元件中的另一个被控制以允许电流流过与另一个是第一个开关元件。此外，允许通过另一个第一开关元件流动的电流足以允许与另一个第一开关元件相关的电路块逻辑操作。

52. 发明授权

US07257725B2 Memory system 失效
标题翻译：内存系统
公开(公告)号：US07257725B2
公开(公告)日：2007-08-14
申请号：US10294594
申请日：2002-11-15
申请人： Hideki Osaka , Toyohiko Komatsu , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
发明人： Hideki Osaka , Toyohiko Komatsu , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
IPC分类号： G06F1/00
CPC分类号： G06F13/4086
摘要： A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.
摘要翻译：时钟位于靠近与存储器控制器并且远离控制器的多个存储器模块的位置，并且执行布线，使得读取访问优先于读取数据的传输。对于写数据，测量对应于每个模块的往返传播延迟时间的延迟量，并且在保持时钟和数据之间的已知时间关系的同时执行写入数据的写入。为了测量往返反射，线路以1：1的关系连接到模块和位置检测电路之间，并且电路测量从具有与有线线路相同阻抗的驱动器的信号输出时间所花费的时间到滞后接收器的反射波接收时间。

53. 发明授权

US07242214B2 Semiconductor integrated circuits with power reduction mechanism 失效
公开(公告)号：US07242214B2
公开(公告)日：2007-07-10
申请号：US11599275
申请日：2006-11-15
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K17/16 , G05F1/10
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

54. 发明申请

US20070057696A1 Semiconductor integrated circuits with power reduction mechanism 失效
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US20070057696A1
公开(公告)日：2007-03-15
申请号：US11599275
申请日：2006-11-15
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/0175
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching-elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
摘要翻译：半导体集成电路芯片的功耗在2.5V或更低的工作电压下工作时，功耗降低。开关元件设置在芯片内的每个电路块中。开关元件的常数被设定为使得其断开状态下的每个开关元件中的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。因此，非有源电路块的耗散电流被限制为相应的开关元件的漏电流值。因此，非有源电路块的耗散电流的总和小于有源电路块中的有功电流。结果，即使在活动状态下，半导体集成电路芯片的功率消耗也可以减小。

55. 发明申请

US20060250876A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060250876A1
公开(公告)日：2006-11-09
申请号：US11483649
申请日：2006-07-11
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C5/14
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

56. 发明申请

US20060139052A1 Semiconductor integrated circuits with power reduction mechanism 有权
公开(公告)号：US20060139052A1
公开(公告)日：2006-06-29
申请号：US11356100
申请日：2006-02-17
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/003
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

57. 发明授权

US07016236B2 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US07016236B2
公开(公告)日：2006-03-21
申请号：US11101504
申请日：2005-04-08
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C16/04
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括多个第一存储器阵列，多个第二存储器阵列，第一电压发生器和多个第一焊盘。半导体芯片被分成第一矩形区域，第二矩形区域和第三矩形区域，并且第三矩形区域被布置在第一矩形区域和第二矩形区域之间。多个第一存储器阵列形成在第一矩形区域中。多个第二存储器阵列形成在第二矩形区域中。电压发生器和多个第一接合焊盘被布置在第三矩形区域中。多个第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和多个第二存储器阵列之间没有布置接合焊盘。

58. 发明申请

US20050237839A1 Semiconductor memory device 有权
公开(公告)号：US20050237839A1
公开(公告)日：2005-10-27
申请号：US11168291
申请日：2005-06-29
申请人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
发明人： Hideharu Yahata , Masashi Horiguchi , Yoshikazu Saitoh , Yasushi Kawase
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

59. 发明申请

US20050219922A1 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US20050219922A1
公开(公告)日：2005-10-06
申请号：US11139513
申请日：2005-05-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：用于制造存储器件的方法，所述存储器是具有备用位线的存储器阵列，并且提供具有冗余电路的缺陷恢复方案。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

60. 发明申请

US20050213414A1 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US20050213414A1
公开(公告)日：2005-09-29
申请号：US11131181
申请日：2005-05-18
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： G11C5/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/0185 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/20
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

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