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    • 60. 发明授权
    • Frequency divider and phase locked loop including the same
    • 分频器和锁相环包括相同的
    • US08736317B2
    • 2014-05-27
    • US13535424
    • 2012-06-28
    • Hwan-Seok YeoJi-Hyun Kim
    • Hwan-Seok YeoJi-Hyun Kim
    • H03K23/00H03K21/00
    • H03K23/52H03K23/667H03L7/089H03L7/18
    • A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.
    • 频率包括:第一边缘检测单元,被配置为响应于检测到输入信号的第一边缘而产生第一计数信号;以及第二边缘检测单元,被配置为产生第二计数信号,所述第二边缘检测单元响应于检测到第一 并且响应于在第二操作模式中检测到输入信号的第二边缘而产生第二计数信号。 第一和第二边缘中的一个是上升沿,第一和第二边缘中的另一个是下降沿。 脉冲触发缓冲器单元响应于第一和第二计数信号产生输出信号。 输出信号相对于作为一个模式的奇数分频比的输入信号和另一模式下的偶数分频比除以目标分频比。