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51. 发明授权

US07987343B2 Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass 失效
标题翻译：处理器和方法用于同步加载多个提取序列和流水线阶段结果跟踪，以促进早期地址生成互锁旁路
公开(公告)号：US07987343B2
公开(公告)日：2011-07-26
申请号：US12051527
申请日：2008-03-19
申请人： Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Chung-Lung Kevin Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Chung-Lung Kevin Shum
IPC分类号： G06F9/40 , G06F9/30
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/3826 , G06F9/3838 , G06F9/3857
摘要： A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.
摘要翻译：一种流水线处理器，包括用于地址生成互锁的架构，所述处理器包括：指令分组单元，用于检测写后依赖关系并解决指令相互依赖性; 指令分配单元（IDU），包括地址生成互锁（AGI）和操作数提取逻辑，用于向至少一个加载存储单元和执行单元分发指令; 其中所述加载存储单元被配置为访问数据高速缓存并且将获取的数据返回到所述执行单元; 其中所述执行单元被配置为将数据写入通用寄存器组; 并且其中所述体系结构提供了对在写入通用寄存器组之前在执行单元中执行这种指令的地址生成的负载多重指令的结果的旁路支持。还提供了一种方法和计算机系统。

52. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

53. 发明授权

US07921279B2 Operand and result forwarding between differently sized operands in a superscalar processor 失效
标题翻译：操作数和结果在超标量处理器中的不同大小的操作数之间转发
公开(公告)号：US07921279B2
公开(公告)日：2011-04-05
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

54. 发明授权

US07913067B2 Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor 失效
标题翻译：用于通过按顺序处理器中的非均匀执行流水线重复执行指令的方法和系统
公开(公告)号：US07913067B2
公开(公告)日：2011-03-22
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

55. 发明申请

US20090241084A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR EXPLOITING ORTHOGONAL CONTROL VECTORS IN TIMING DRIVEN SYSTEMS 有权
标题翻译：方法，系统和计算机程序产品在时序驱动系统中开发正交控制矢量
公开(公告)号：US20090241084A1
公开(公告)日：2009-09-24
申请号：US12051268
申请日：2008-03-19
申请人： Edward T. Malley , Fadi Y. Busaba , David S. Hutton , Christopher A. Krygowski , Jeffrey S. Plate , John G. Rell
发明人： Edward T. Malley , Fadi Y. Busaba , David S. Hutton , Christopher A. Krygowski , Jeffrey S. Plate , John G. Rell
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the logic cone, obtaining logical solutions and selecting a solution from the logical solutions.
摘要翻译：用于在正时驱动系统中利用正交控制矢量的系统，方法和计算机程序产品。示例性实施例包括运行系统上的初始逻辑合成运行，识别与运行相关的逻辑锥的关键输入，识别逻辑锥中的正交矢量，向矢量添加矢量，获得逻辑解并从逻辑解决方案。

56. 发明申请

US20090240914A1 RECYCLING LONG MULTI-OPERAND INSTRUCTIONS 失效
标题翻译：回收长时间的多操作指令
公开(公告)号：US20090240914A1
公开(公告)日：2009-09-24
申请号：US12051215
申请日：2008-03-19
申请人： Edward T. Malley , Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum
发明人： Edward T. Malley , Khary J. Alexander , Fadi Y. Busaba , Vimal M. Kapadia , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/30065 , G06F9/3832
摘要： A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.
摘要翻译：公开了配置用于长操作数指令的流水线微处理器。微处理器包括存储单元和加载存储单元。加载存储单元耦合到存储器单元，并且包括从存储器单元接收信息并包括操作数选择器和移位寄存器部分的数据格式化器。微处理器还包括耦合到加载存储单元并从其接收操作数信息的执行单元。执行单元包括耦合到执行单元内的存储位置的输出锁存器，用于存储来自执行单元的输出信息。

57. 发明授权

US07200742B2 System and method for creating precise exceptions 失效
标题翻译：用于创建精确异常的系统和方法
公开(公告)号：US07200742B2
公开(公告)日：2007-04-03
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
IPC分类号： G06F9/38
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译：一种用于创建精确异常的方法，包括检查指向引起异常的指令。检查点导致当前检查点状态。当前检查点状态被锁定。确定多个寄存器中的任一个是否需要恢复到当前检查点状态。响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

58. 发明授权

US07167968B2 Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data 有权
标题翻译：用于打包十进制数据的存储预对齐和EBCDIC，ASCII和unicode基本拉丁转换
公开(公告)号：US07167968B2
公开(公告)日：2007-01-23
申请号：US10834637
申请日：2004-04-29
申请人： Fadi Y. Busaba , Steven R. Carlough , Mark A. Check , Christopher A. Krygowski , John G. Rell, Jr. , Frank Tanzi
发明人： Fadi Y. Busaba , Steven R. Carlough , Mark A. Check , Christopher A. Krygowski , John G. Rell, Jr. , Frank Tanzi
IPC分类号： G06F12/06
CPC分类号： G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F12/0886
摘要： A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal hardware in a microprocessor designed to generate decimal results. Converting from Packed Decimal to ASCII and Unicode Basic Latin is necessary to report Decimal Arithmetic results in a required format for the application program. To further improve performance, all available write ports in the fixed point unit (FXU) are utilized to reduce the number of cycles necessary to store results. To prevent data fetching of the unused destination data from slowing down instruction execution, the destination locations are tested for storage access exceptions, but the data for these operands are not actually fetched. A single read request from the FXU to the operand buffers effectively reads the entire destination address (up to 8 double-words of data) in a single cycle.
摘要翻译：在指令执行期间预先对准用于存储的数据的方法通过消除数据对准所需的周期来提高性能。该方法可以在ASCII和Packed Decimal格式之间以及Unicode Basic Latin和Packed Decimal格式之间转换数据。转换为打包十进制硬件需要十进制格式，用于生成十进制结果的微处理器。从包装十进制转换为ASCII和Unicode基本拉丁文需要以应用程序所需的格式报告十进制算术结果。为了进一步提高性能，利用固定点单元（FXU）中的所有可用写入端口来减少存储结果所需的周期数。为了防止数据获取未使用的目标数据缓慢的指令执行，目标位置被测试存储访问异常，但是这些操作数的数据实际上并没有被提取。从FXU到操作数缓冲区的单个读取请求在单个周期中有效读取整个目标地址（最多8个双字的数据）。

59. 发明授权

US07167889B2 Decimal multiplication for superscaler processors 失效
标题翻译：超标量处理器的十进制乘法
公开(公告)号：US07167889B2
公开(公告)日：2007-01-23
申请号：US10436392
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
IPC分类号： G06F7/523
CPC分类号： G06F9/3001 , G06F7/496
摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.
摘要翻译：一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

60. 发明授权

US07010676B2 Last iteration loop branch prediction upon counter threshold and resolution upon counter one 失效
标题翻译：最后迭代循环分支预测在计数器阈值和分辨率之间
公开(公告)号：US07010676B2
公开(公告)日：2006-03-07
申请号：US10436296
申请日：2003-05-12
申请人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
发明人： Fadi Y. Busaba , Klaus J. Getzlaff , Christopher A. Krygowski , Timothy J. Slegel
IPC分类号： G06F9/38
CPC分类号： G06F9/325 , G06F9/3844
摘要： An embodiment of the invention is a processor for processing loop branch instructions. The processor includes an instruction unit for fetching and decoding instructions including at least one loop branch instruction. A branch prediction unit predicts target instructions to be fetched and decoded by the instruction unit in response to the loop branch instruction. An execution unit executes instructions from the instruction unit and maintains a counter indicating an iteration of a loop. The execution unit includes detection logic for detecting when the counter equals a threshold and notifies the branch prediction unit when the counter equals the threshold.
摘要翻译：本发明的实施例是用于处理回路分支指令的处理器。所述处理器包括用于对包括至少一个环路分支指令的指令进行读取和解码的指令单元。分支预测单元响应于循环分支指令预测由指令单元获取和解码的目标指令。执行单元从指令单元执行指令，并且维护指示循环迭代的计数器。执行单元包括用于检测计数器何时等于阈值的检测逻辑，并且当计数器等于阈值时通知分支预测单元。

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