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51. 发明授权

US07117389B2 Multiple processor core device having shareable functional units for self-repairing capability 失效
标题翻译：具有用于自修复能力的可共享功能单元的多处理器核心设备
公开(公告)号：US07117389B2
公开(公告)日：2006-10-03
申请号：US10667084
申请日：2003-09-18
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2035 , G06F11/2051
摘要： Multiple processor cores are implemented on a single integrated circuit chip, each having its own respective shareable functional units, which are preferably floating point units. A failure of a shareable unit in one processor causes that processor to share the corresponding unit in another processor on the same chip. Preferably, a functional unit is shared on a cycle interleaved basis.
摘要翻译：多个处理器核实现在单个集成电路芯片上，每个集成电路芯片具有各自的可共享功能单元，其优选地是浮点单元。一个处理器中的可共享单元的故障导致该处理器在同一芯片上的另一个处理器中共享相应的单元。优选地，在循环交织的基础上共享功能单元。

52. 发明授权

US07099999B2 Apparatus and method for pre-fetching data to cached memory using persistent historical page table data 失效
标题翻译：使用持久性历史页表数据预取数据到缓存存储器的装置和方法
公开(公告)号：US07099999B2
公开(公告)日：2006-08-29
申请号：US10675732
申请日：2003-09-30
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F12/00 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F2212/6024 , G06F2212/654
摘要： A computer system includes a main memory, at least one processor, and at least one level of cache. The system maintains reference history data with respect to each addressable page in memory, preferably in a page table. The reference history data is preferably used to determine which cacheable sub-units of the page should be pre-fetched to the cache. The reference history data is preferably an up or down counter which is incremented if the cacheable sub-unit is loaded into cache and is referenced by the processor, and decremented if the sub-unit is loaded into cache and is not referenced before being cast out. The reference counter thus expresses an approximate likelihood, based on recent history, that the sub-unit will be referenced in the near future.
摘要翻译：计算机系统包括主存储器，至少一个处理器和至少一个级别的高速缓存。该系统相对于存储器中的每个可寻址页面优选地在页表中维护参考历史数据。参考历史数据优选地用于确定页面的哪些可高速缓存的子单元应该被预取到高速缓存。参考历史数据优选地是一个向上或向下计数器，如果可高速缓存的子单元被加载到高速缓存中并被处理器引用，则其递增，并且如果子单元被加载到高速缓存中并且在被抛出之前未被引用则递减。因此，参考计数器基于最近的历史来表示近似可能性，即在不久的将来将引用子单元。

53. 发明授权

US07086058B2 Method and apparatus to eliminate processor core hot spots 失效
公开(公告)号：US07086058B2
公开(公告)日：2006-08-01
申请号：US10163968
申请日：2002-06-06
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F9/46 , G06F15/00 , G06F11/00 , G01K15/00 , H02H5/04 , G06F13/24
CPC分类号： G06F9/4881 , G06F1/206 , G06F9/5094 , G06F2209/5014 , Y02D10/22
摘要： Methods and apparatus are provided for eliminating hot spots on processor chips in a symmetric multiprocessor (SMP) computer system. Some operations, in particular, floating point multiply/add, repetitively utilize portions of a processor chip to the point that the average power of the affected portions exceeds cooling capabilities. The localized temperature of the affected portions can then exceed design limits. The current invention determines when a hot spot occurs and task swaps the task to another processor prior to the localized temperature becoming too hot. Moving of tasks to processors that have data affinity with the processor reporting a hot spot is considered. Further considerations include prioritizing unused processors and those processors that have not recently reported a hot spot.

54. 发明授权

US06990510B2 Wide adder with critical path of three gates 失效
公开(公告)号：US06990510B2
公开(公告)日：2006-01-24
申请号：US10054065
申请日：2002-01-22
申请人： David Michael Friend , David Arnold Luick , Nghia Van Phan
发明人： David Michael Friend , David Arnold Luick , Nghia Van Phan
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/3872
摘要： Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

55. 发明授权

US06941421B2 Zero delay data cache effective address generation 失效
标题翻译：零延迟数据缓存有效地址生成
公开(公告)号：US06941421B2
公开(公告)日：2005-09-06
申请号：US10282519
申请日：2002-10-29
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F12/08 , G06F9/355 , G06F12/00 , G06F12/02
CPC分类号： G06F9/355 , G06F12/0802
摘要： A method and system for accessing a specified cache line using previously decoded base address offset bits, stored with a register file, which eliminate the need to perform a full address decode in the cache access path, and to replace the address generation adder multiple level logic with only one level of rotator/multiplexer logic. The decoded base register offset bits enable the direct selection of the specified cache line, thus negating the need for the addition and the decoding of the base register offset bits at each access to the cache memory. Other cache lines are accessed by rotating the decoded base address offset bits, resulting in a selection of another cache word line.
摘要翻译：一种使用先前解码的基地址偏移位访问指定高速缓存行的方法和系统，其存储有寄存器文件，其消除了在高速缓存访问路径中执行全地址解码的需要，并且替换地址生成加法器多级逻辑只有一级旋转器/多路复用器逻辑。解码的基址寄存器偏移位使得能够直接选择指定的高速缓存行，从而不需要在对高速缓冲存储器的每次访问时对基址寄存器偏移位的加法和解码。通过旋转解码的基地址偏移位来访问其他高速缓存行，导致另一高速缓存字线的选择。

56. 发明授权

US06775735B2 Instruction pair detection and pseudo ports for cache array 失效
公开(公告)号：US06775735B2
公开(公告)日：2004-08-10
申请号：US09974955
申请日：2001-10-11
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F12/0851
摘要： Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.

57. 发明授权

US06763421B2 Instruction pair detection and pseudo ports for cache array 失效
标题翻译：缓存阵列的指令对检测和伪端口
公开(公告)号：US06763421B2
公开(公告)日：2004-07-13
申请号：US09975405
申请日：2001-10-11
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3885 , G06F12/0848
摘要： Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.
摘要翻译：提供了其中并行执行第一和第二指令的实施例。分别根据第一和第二指令生成第一和第二地址。第一地址用于从数据高速缓存行中选择数据高速缓存RAM和第一数据库的数据高速缓存行。第二个地址用于从数据高速缓存中选择第二个数据库。从数据高速缓存RAM并行地输出第一和第二数据组。指令对测试电路测试第一和第二指令访问数据高速缓存RAM的相同数据高速缓存行的概率。如果两个指令不太可能访问相同的数据高速缓存行，则第二指令被重新执行并重新执行，并且不使用第二数据库。

58. 发明授权

US5872990A Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment 失效
标题翻译：通过多处理环境中的回滚重新排序内存引用操作和冲突解决
公开(公告)号：US5872990A
公开(公告)日：1999-02-16
申请号：US779071
申请日：1997-01-07
申请人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
发明人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
IPC分类号： G06F9/38 , G06F9/45 , G06F9/46
CPC分类号： G06F9/52 , G06F8/445 , G06F9/3834 , G06F9/3863
摘要： Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.
摘要翻译：在多处理系统中使用编译和/或运行时指令调度来重新排序存储器访问指令，使得以对编程器透明的方式来模拟强烈一致的编程模型。多处理系统检测潜在的共享内存冲突，通过在预先存储在回滚寄存器组中的预定先前状态下重新启动受影响的处理单元的操作，以及从该状态恢复指令执行来避免这些冲突。

59. 发明申请

US20090006818A1 Method and Apparatus for Multiple Load Instruction Execution 失效
标题翻译：多重加载指令执行的方法和装置
公开(公告)号：US20090006818A1
公开(公告)日：2009-01-01
申请号：US11769271
申请日：2007-06-27
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/382 , G06F9/3824 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3869 , G06F9/3889
摘要： A method and apparatus for executing instructions. The method includes receiving a first load instruction and a second load instruction. The method also includes issuing the first load instruction and the second load instruction to a cascaded delayed execution pipeline unit having at least a first execution pipeline and a second execution pipeline, wherein the second execution pipeline executes an instruction in a common issue group in a delayed manner relative to another instruction in the common issue group executed in the first execution pipeline. The method also includes accessing a cache by executing the first load instruction and the second load instruction. A delay between execution of the first load instruction and the second load instruction allows the cache to complete the access with the first load instruction before beginning the access with the second load instruction.
摘要翻译：一种用于执行指令的方法和装置。该方法包括接收第一加载指令和第二加载指令。该方法还包括向具有至少第一执行流水线和第二执行流水线的级联延迟执行流水线单元发出第一加载指令和第二加载指令，其中第二执行流水线在延迟的第一执行流水线中执行指令，方式相对于在第一执行管线中执行的共同问题组中的另一指令。该方法还包括通过执行第一加载指令和第二加载指令来访问高速缓存。执行第一加载指令和第二加载指令之间的延迟允许高速缓存在开始使用第二加载指令的访问之前用第一加载指令完成访问。

60. 发明申请

US20090006803A1 L2 Cache/Nest Address Translation 审中-公开
标题翻译： L2缓存/巢地址转换
公开(公告)号：US20090006803A1
公开(公告)日：2009-01-01
申请号：US11769978
申请日：2007-06-28
申请人： David Arnold Luick
发明人： David Arnold Luick
IPC分类号： G06F9/26
CPC分类号： G06F12/0897 , G06F12/1045
摘要： A method and apparatus for accessing cache memory in a processor. The method includes accessing requested data in one or more level one caches of the processor using requested effective addresses of the requested data. If the one or more level one caches of the processor do not contain requested data corresponding to the requested effective addresses, the requested effective addresses are translated to real addresses. A lookaside buffer includes a corresponding entry for each cache line in each of the one or more level one caches of the processor. The corresponding entry indicates a translation from the effective addresses to the real addresses for the cache line. The translated real addresses are used to access a level two cache.
摘要翻译：一种用于在处理器中访问高速缓冲存储器的方法和装置。该方法包括使用所请求数据的所请求的有效地址访问处理器的一个或多个一级缓存中的请求数据。如果处理器的一个或多个一级缓存不包含对应于所请求的有效地址的请求数据，则所请求的有效地址被转换为实际地址。后视缓冲器包括处理器的一个或多个一级高速缓存中的每一个中的每个高速缓存行的相应条目。相应的条目表示从有效地址到高速缓存行的实际地址的转换。翻译的实际地址用于访问二级缓存。

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