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    • 55. 发明授权
    • Magnetic tunnel junction for MRAM applications
    • 用于MRAM应用的磁隧道结
    • US08786036B2
    • 2014-07-22
    • US12930877
    • 2011-01-19
    • Wei CaoCheng T. HorngWitold KulaChyu Jiuh Torng
    • Wei CaoCheng T. HorngWitold KulaChyu Jiuh Torng
    • H01L43/10H01L27/22
    • H01L43/10G11C11/161H01L27/222H01L43/00H01L43/02H01L43/08
    • A MTJ in an MRAM array is disclosed with a composite free layer having a lower crystalline layer contacting a tunnel barrier and an upper amorphous NiFeX layer for improved bit switching performance. The crystalline layer is Fe, Ni, or FEB with a thickness of at least 6 Angstroms which affords a high magnetoresistive ratio. The X element in the NiFeX layer is Mg, Hf, Zr, Nb, or Ta with a content of 5 to 30 atomic % NiFeX thickness is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. In an alternative embodiments, the crystalline layer may be a Fe/NiFe bilayer. Optionally, the amorphous layer may have a NiFeM1/NiFeM2 configuration where M1 and M2 are Mg, Hf, Zr, Nb, or Ta, and M1 is unequal to M2. Annealing at 300° C. to 360° C. provides a high magnetoresistive ratio of about 150%.
    • 公开了具有接触隧道势垒的较低结晶层和上部非晶NiFeX层的复合自由层的MRAM阵列中的MTJ,用于改善位切换性能。 结晶层是厚度至少为6埃的Fe,Ni或FEB,其具有高的磁阻比。 NiFeX层中的X元素为含有5〜30原子%NiFeX厚度的Mg,Hf,Zr,Nb或Ta优选为20〜40埃,以显着降低位线切换电流和短路位数。 在替代实施例中,结晶层可以是Fe / NiFe双层。 可选地,非晶层可以具有其中M1和M2是Mg,Hf,Zr,Nb或Ta的NiFeM1 / NiFeM2构型,M1不等于M2。 在300℃至360℃退火,提供约150%的高磁阻比。
    • 58. 发明申请
    • Method to Reduce Magnetic Film Stress for Better Yield
    • 减少磁膜应力以获得更好的产量的方法
    • US20130302912A1
    • 2013-11-14
    • US13469258
    • 2012-05-11
    • Tom ZhongKenlin HuangChyu-Jiuh Torng
    • Tom ZhongKenlin HuangChyu-Jiuh Torng
    • H01L21/02
    • H01L43/12H01L43/08
    • A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.
    • 在晶片级CMOS衬底上形成诸如MTJ(磁性隧道结)层的薄膜沉积的方法,使得薄膜沉积被壁或沟槽分段,并且不受薄膜应力的影响 晶圆翘曲或其他后续退火工艺。 在CMOS衬底上形成界面层,并且通过形成延伸到其上表面的底切沟槽或通过制造沿其上表面延伸的T形壁而被图案化。 薄膜连续地沉积在图案化表面上,于是沟槽或壁分隔沉积物并用作应力消除机制,以消除作为诸如由晶片翘曲引起的应力的加工的不利影响。