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51. 发明申请

US20150169439A1 ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM 有权
标题翻译：在多级存储器系统中的异步代理数据引导
公开(公告)号：US20150169439A1
公开(公告)日：2015-06-18
申请号：US14133097
申请日：2013-12-18
申请人： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
发明人： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
IPC分类号： G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G06F12/126
摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.
摘要翻译：处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

52. 发明授权

US09053251B2 Providing a sideband message interface for system on a chip (SoC) 有权
标题翻译：为芯片上的系统提供边带消息接口（SoC）
公开(公告)号：US09053251B2
公开(公告)日：2015-06-09
申请号：US13306244
申请日：2011-11-29
申请人： Robert P. Adler , Eran Tamari , Mikal C. Hunsaker , Sridhar Lakshmanamurthy , Michael T. Klinglesmith , Blaise Fanning
发明人： Robert P. Adler , Eran Tamari , Mikal C. Hunsaker , Sridhar Lakshmanamurthy , Michael T. Klinglesmith , Blaise Fanning
IPC分类号： G06F13/14 , G06F13/42 , G06F13/366 , G06F13/40
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/4036
摘要： According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.
摘要翻译：根据一个实施例，芯片上的系统包括每个对应于知识产权（IP）逻辑的多个代理和用于耦合代理的结构。该结构可以包括主消息接口和边带消息接口。该结构还包括一个或多个路由器，以经由该边带消息接口在代理之间提供带外通信。为了实现这种通信，路由器可以执行用于边带消息的基于个人计算机（PC）的规范的排序规则的子集。描述和要求保护其他实施例。

53. 发明申请

US20150006805A1 HYBRID MULTI-LEVEL MEMORY ARCHITECTURE 有权
标题翻译：混合多级存储器架构
公开(公告)号：US20150006805A1
公开(公告)日：2015-01-01
申请号：US13931701
申请日：2013-06-28
申请人： DANNIE G. FEEKES , SHLOMO RAIKIN , BLAISE FANNING , JOYDEEP RAY , JULIUS MANDELBLAT , ARIEL BERKOVITS , ERAN SHIFER , ZVIKA GREENFIELD , EVGENY BOLOTIN
发明人： DANNIE G. FEEKES , SHLOMO RAIKIN , BLAISE FANNING , JOYDEEP RAY , JULIUS MANDELBLAT , ARIEL BERKOVITS , ERAN SHIFER , ZVIKA GREENFIELD , EVGENY BOLOTIN
IPC分类号： G06F3/06
CPC分类号： G06F12/0893 , G06F1/32 , G06F1/3275 , G06F12/063 , G06F12/08 , G06F12/0866 , G06F2212/205 , G06F2212/206 , G06F2212/281 , G06F2212/604 , G06F2212/608 , Y02D10/13 , Y02D10/14
摘要： Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.
摘要翻译：描述了混合多层存储器架构技术。片上系统（SOC）包括多个功能单元和耦合到功能单元的多级存储器控制器（MLMC）。 MLMC耦合到混合多级存储器架构，其包括位于SOC的封装上的第一级动态随机存取存储器（近似存储器）和位于该存储器的二级DRAM（远存储器））的混合多级存储器架构 SOC的脱离包装。 MLMC将第一级DRAM和第二级DRAM作为连续可寻址存储空间，并将第一级DRAM提供给软件，作为第二级DRAM存储容量的附加存储容量。第一级DRAM不存储二级DRAM的内容副本。

54. 发明授权

US08713240B2 Providing multiple decode options for a system-on-chip (SoC) fabric 有权
标题翻译：为片上系统（SoC）架构提供多种解码选项
公开(公告)号：US08713240B2
公开(公告)日：2014-04-29
申请号：US13248263
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Robert P. Adler
IPC分类号： G06F13/42 , G06F13/36 , G06F13/00 , G06F9/26 , G06F11/00
CPC分类号： G06F13/364 , G06F13/28 , G06F13/385 , G06F13/4027 , G06F2213/0026
摘要： In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统级芯片（SoC）可以被配置为在耦合到主代理的结构中接收来自主代理的请求，响应于所选择的请求向主代理发送显示命令授予接收与结构中的请求相对应的事务的命令部分，并且基于命令部分确定接收事务的目标代理，然后向事务的主代理发送事务授权。描述和要求保护其他实施例。

55. 发明授权

US08713234B2 Supporting multiple channels of a single interface 有权
标题翻译：支持单个接口的多个通道
公开(公告)号：US08713234B2
公开(公告)日：2014-04-29
申请号：US13248270
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
IPC分类号： G06F13/36
CPC分类号： G06F13/364 , G06F9/44 , G06F13/362 , G06F15/16
摘要： In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从结构中的第一代理接收对交易的请求并获得交易的地址，请求者标识符，标签和业务类别的方法，以及确定基于至少两个地址，请求者标识符，标签和流量类来接收交易的目标代理。基于该通道确定，可以将事务发送到目标代理的通道。描述和要求保护其他实施例。

56. 发明申请

US20140115219A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 有权
公开(公告)号：US20140115219A1
公开(公告)日：2014-04-24
申请号：US14144309
申请日：2013-12-30
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee
IPC分类号： G06F13/40
CPC分类号： G06F13/4068 , A47K7/028 , G06F13/4273 , G06F2213/0026
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.

57. 发明申请

US20140095859A1 APPARATUS AND METHOD FOR MANAGING REGISTER INFORMATION IN A PROCESSING SYSTEM 有权
标题翻译：在处理系统中管理寄存器信息的装置和方法
公开(公告)号：US20140095859A1
公开(公告)日：2014-04-03
申请号：US14008196
申请日：2011-10-01
申请人： Blaise Fanning , Anil Sabbavarapu
发明人： Blaise Fanning , Anil Sabbavarapu
IPC分类号： G06F9/445
CPC分类号： G06F9/44505 , G06F11/1441 , Y02D10/43
摘要： The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.
摘要翻译：配置寄存器中的设置基于存储在管理寄存器中的值和/或基于在调试操作期间产生复位信号或检测电子系统中的故障或功率状态转换来进行控制。管理寄存器可以向每个配置寄存器分配一个位，并且将根据该位的值来控制要加载到配置寄存器中的设置。另外或替代地，当复位信号呈现指示要存储默认设置的值时，可以控制配置寄存器中的设置。

58. 发明申请

US20130254451A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
公开(公告)号：US20130254451A1
公开(公告)日：2013-09-26
申请号：US13730024
申请日：2012-12-28
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee
IPC分类号： G06F13/42
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.

59. 发明申请

US20090172429A1 POWER MODE CONTROL METHOD AND CIRCUITRY 有权
标题翻译：电源模式控制方法和电路
公开(公告)号：US20090172429A1
公开(公告)日：2009-07-02
申请号：US11967920
申请日：2007-12-31
申请人： Ramana Rachakonda , Blaise Fanning , Anil K. Sabbavarapu , Belliappa M. Kuttanna , Rajesh Patel , Kenneth D. Shoemaker , Lance E. Hacking , Bruce L. Fleming , Ashish V. Choubal
发明人： Ramana Rachakonda , Blaise Fanning , Anil K. Sabbavarapu , Belliappa M. Kuttanna , Rajesh Patel , Kenneth D. Shoemaker , Lance E. Hacking , Bruce L. Fleming , Ashish V. Choubal
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.
摘要翻译：在一些实施例中，提供上电（或功率模式）接口，由此芯片的上电信号被编码为多个状态以提供比用于定义状态的信号的数量更多的功能。

60. 发明申请

US20080162766A1 SIGNAL TECHNIQUES FOR BUS INTERFACES 审中-公开
标题翻译：总线接口信号技术
公开(公告)号：US20080162766A1
公开(公告)日：2008-07-03
申请号：US11618509
申请日：2006-12-29
申请人： Blaise Fanning , Chris Matthews , Chunyu Zhang
发明人： Blaise Fanning , Chris Matthews , Chunyu Zhang
IPC分类号： G06F13/14
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include a configuration module and a driver module. The configuration module establishes an operational mode setting from a first operational mode and a second operational mode. The driver module may operate according to this setting. For instance, according to the first operational mode, the driver module continually drives an interconnection medium. However, for the second operational mode, the driver module drives the interconnection medium when it receives an input signal and otherwise refrains from driving the interconnection medium. According to the first operational mode, a termination module may couple a pull-up resistance to the interconnection medium. However, for the second operational mode, the termination module does not couple such a resistance to the interconnection medium.
摘要翻译：公开了涉及通过互连介质传送信号的技术。例如，设备可以包括配置模块和驱动器模块。配置模块从第一操作模式和第二操作模式建立操作模式设置。驱动器模块可以根据此设置进行操作。例如，根据第一操作模式，驱动器模块连续驱动互连介质。然而，对于第二操作模式，当接收到输入信号并且禁止驱动互连介质时，驱动器模块驱动互连介质。根据第一操作模式，终端模块可以将上拉电阻耦合到互连介质。然而，对于第二操作模式，终端模块不将这种电阻耦合到互连介质。

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