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    • 51. 发明授权
    • Group delay correction method and apparatus
    • 组延迟校正方法和装置
    • US5896306A
    • 1999-04-20
    • US787203
    • 1997-01-22
    • Felix Aschwanden
    • Felix Aschwanden
    • H04B1/30H04L25/03H04L27/00H04L27/233H04B1/10
    • H04L25/03133H04L27/2332H04B1/30H04L2027/0028H04L2027/0046H04L2027/0057
    • A filtering method and apparatus in which an input signal is subjected to an analog filtering step, then an analog to digital conversion step and finally a digital filtering step to produce a filtered output signal. The pulse response of the digital filter is the mirror image of the pulse response of the analog filter and the cascaded filtering steps result in a filtered output signal which exhibits little or no group delay or phase distortion. The digital filter may be a FIR filter. Also disclosed is a phase error correction method whereby a pulse is inserted into a circuit or data stream prior to a group delay imparting device or function, a pulse response of the group delay imparting device or function is measured prior to a phase correcting device or function, mirror image filter coefficients are calculated using a window function and then incorporated into a phase correcting filter arrangement.
    • 一种滤波方法和装置,其中对输入信号进行模拟滤波步骤,然后进行模数转换步骤,最后是数字滤波步骤以产生经滤波的输出信号。 数字滤波器的脉冲响应是模拟滤波器的脉冲响应的镜像,并且级联滤波步骤导致显示很少或没有组延迟或相位失真的滤波输出信号。 数字滤波器可以是FIR滤波器。 还公开了一种相位误差校正方法,其中在组延迟赋予装置或功能之前将脉冲插入电路或数据流中,在相位校正装置或功能之前测量组延迟赋予装置或功能的脉冲响应 ,使用窗口函数计算镜像滤波器系数,然后并入相位校正滤波器装置。
    • 52. 发明授权
    • Charge controlled raster correction circuit
    • 电荷控制光栅校正电路
    • US5841248A
    • 1998-11-24
    • US846342
    • 1997-04-30
    • Peter Eduard HaferlRudolf Weber
    • Peter Eduard HaferlRudolf Weber
    • H04N3/23G09G1/00G09G1/04H04N3/223H04N3/233H01J29/56
    • H04N3/223H04N3/233
    • An East-West switching transistor is coupled between a flyback transformer primary winding and a horizontal deflection output transistor circuit to control retrace energy to obtain an East-West modulation of the deflection current amplitude as required for East-West pincushion raster correction. A pair of series coupled first and second capacitors forming a capacitive voltage divider are coupled to a retrace resonant circuit that includes the deflection winding via a sampling switch, during a first half of a retrace interval, to produce a first ramping capacitor voltage in the first capacitor from a portion of a retrace pulse voltage. The first capacitor is coupled to an East-West pincushion raster correction current source for producing a second ramping capacitor voltage in the first capacitor that ramps in an opposite direction. A comparator is responsive to the capacitor voltage for controlling a conduction interval of the East-West switching transistor.
    • 东西开关晶体管耦合在反激式变压器初级绕组和水平偏转输出晶体管电路之间,以控制回扫能量,以获得东西枕形光栅校正所需的偏转电流幅度的东西调制。 形成电容性分压器的一对串联耦合的第一和第二电容器在回扫间隔的前半部分期间经由采样开关耦合到回扫谐振电路,该回扫谐振电路包括偏转绕组,以产生第一斜波电容器电压 电容器从回扫脉冲电压的一部分。 第一电容器耦合到东西枕形光栅校正电流源,用于在第一电容器中产生相反方向斜坡的第二斜坡电容器电压。 比较器响应于电容器电压来控制东西开关晶体管的导通间隔。
    • 60. 发明授权
    • Raster distortion avoidance arrangement
    • 光栅失真避免安排
    • US5402044A
    • 1995-03-28
    • US70824
    • 1993-06-03
    • Peter E. Haferl
    • Peter E. Haferl
    • H04N3/22H04N3/233H01J29/56
    • H04N3/22H04N3/233
    • Organ pipes distortions, caused by parasitic ringing in a horizontal deflection current are suppressed by forming a current pulse in a current injection arrangement. The current pulse is coupled to a junction terminal between a terminal of the horizontal deflection winding where a high retrace pulse voltage is developed and a low voltage terminal of a linearity correction inductance. A high voltage terminal of the linearity correction inductance is coupled to a horizontal output transistor. The current pulse begins prior to the end of retrace and ends during the trace interval. A modulation network is coupled across the linearity correction inductance for providing a low impedance current path to the current pulse.
    • 通过在电流注入装置中形成电流脉冲来抑制由水平偏转电流中的寄生振荡引起的器管变形。 电流脉冲耦合到高回波脉冲电压产生的水平偏转绕组的端子与线性校正电感的低电压端之间的结端子。 线性校正电感的高电压端子耦合到水平输出晶体管。 当前脉冲在回扫结束之前开始,并在跟踪间隔期间结束。 调制网络跨线性校正电感耦合,以提供到当前脉冲的低阻抗电流路径。