专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US6154640A Method and apparatus for communication and signal synthesis 失效
标题翻译：用于通信和信号合成的方法和装置
公开(公告)号：US6154640A
公开(公告)日：2000-11-28
申请号：US532049
申请日：1995-09-21
申请人： Kenji Itoh , Ken'ichi Tajima , Shuji Nishimura , Akio Iida
发明人： Kenji Itoh , Ken'ichi Tajima , Shuji Nishimura , Akio Iida
IPC分类号： H03B28/00 , H03D7/16 , H03J7/06 , H03L7/107 , H03L7/16 , H03L7/18 , H03L7/183 , H03L7/185 , H03L7/23 , H04B1/26 , H04B1/30 , H04B1/3822 , H04B1/40 , H01Q11/12
CPC分类号： H03L7/107 , H03D7/161 , H03L7/1806 , H03L7/23
摘要： In a receiving and transmitting apparatus, a frequency of a direct digital synthesizer provided in a local oscillating circuit is controlled in order to reduce a frequency error, based on data of a frequency error detecting circuit. The direct digital synthesizer includes a digital operation circuit for inputting data designating the frequency and outputting an amplitude value of a periodic signal synchronous with a reference clock, and digital-analog converter for converting the amplitude value of the periodic signal to an analog signal.
摘要翻译：在接收和发送装置中，基于频率误差检测电路的数据，控制设置在本地振荡电路中的直接数字合成器的频率，以便减少频率误差。直接数字合成器包括数字运算电路，用于输入指定频率的数据并输出与参考时钟同步的周期信号的振幅值;以及数模转换器，用于将周期信号的振幅值转换为模拟信号。

42. 发明授权

US6122326A High precision, low phase noise synthesizer with vector modulator 失效
公开(公告)号：US6122326A
公开(公告)日：2000-09-19
申请号：US895445
申请日：1997-07-15
申请人： Thomas Jackson , David Bourner , Hai Tang
发明人： Thomas Jackson , David Bourner , Hai Tang
IPC分类号： H03B27/00 , H03B28/00 , H03C3/09 , H03C5/00 , H03D7/00 , H03L7/18 , H03L7/23 , H04L27/20
CPC分类号： H03L7/23 , H03C3/0908 , H03C3/0983 , H03D7/00 , H03B27/00 , H03B28/00 , H03C5/00 , H03L7/1806
摘要： An apparatus for generating a modulated signal which includes a modulator operative for receiving a first signal and input data signals, and modulating the first signal in accordance with the input data signals so as to produce a modulated reference signal; a first frequency divider coupled to the modulator output, operative to reduce the frequency of the modulated reference signal by a predetermined factor; a signal generator operative to produce a second signal; a first mixer having a first input coupled to an output of the first frequency divider and a second input coupled to the output of the signal generator. The first mixer operates to frequency translate the modulated reference signal by an amount equal to the frequency of the second signal. In addition, the signal generator of the present invention contains a direct digital synthesizer coupled to a second phase lock loop which operates to up-convert the output signal of the DDS to the microwave region. The feedback network of the second phase lock loop utilizes frequency translation to down-convert the output signal in order to close the loop.

43. 发明授权

US6028412A Digital frequency generator 有权
标题翻译：数字频率发生器
公开(公告)号：US6028412A
公开(公告)日：2000-02-22
申请号：US101011
申请日：1998-08-04
申请人： Thomas Adam Shine , Ian Basil Shine
发明人： Thomas Adam Shine , Ian Basil Shine
IPC分类号： H02P8/00 , A61M5/172 , G06F1/02 , H02P8/14 , H03B28/00 , H03L7/16
CPC分类号： A61M5/172 , H02P8/14 , H03B28/00
摘要： Generating a clock signal having a desired frequency is accomplished by generating a pulse each time a stored accumulator value is found to be greater than or equal to a stored trigger value The seored accumulator value is incremented by a first iterative value n (r) until the stored accumulator value is greater than or equal to the stored trigger value. Subsequently, the stored accumulator value is decremented by a second iterative value until the stored accumulator value is less than the stored trigger value. During each iteration incrementing the stored accumulator value, a current frequency of the clock spinal is compared to a desired frequency value, and if the two values are different, the first iterative value (r) is corrected by a predetermined rate over one or more subsequent iterations until the frequency of the generator clock signal corresponds to the detected value of the desired frequency.
摘要翻译： PCT No.PCT / GB96 / 03240 Sec。 371日期：1998年4月8日 102（e）日期1998年8月4日PCT 1996年12月27日PCT公布。公开号WO97 / 24797 日期1997年7月10日发现具有期望频率的时钟信号通过每当存储的累加器值被发现大于或等于存储的触发值时产生脉冲来实现。所述累加器值增加第一迭代值n （r），直到存储的累加器值大于或等于存储的触发值。随后，存储的累加器值减少第二迭代值，直到存储的累加器值小于存储的触发值。在每次迭代期间增加存储的累加器值，将时钟脊线的当前频率与期望的频率值进行比较，并且如果两个值不同，则第一迭代值（r）在一个或多个随后的迭代直到发生器时钟信号的频率对应于所需频率的检测值。

44. 发明授权

US5952895A Direct digital synthesis of precise, stable angle modulated RF signal 失效
标题翻译：直接数字合成精确，稳定的角度调制RF信号
公开(公告)号：US5952895A
公开(公告)日：1999-09-14
申请号：US27954
申请日：1998-02-23
申请人： Earl W. McCune, Jr. , Wendell Sander
发明人： Earl W. McCune, Jr. , Wendell Sander
IPC分类号： H03C3/00 , H03B28/00 , H03C3/08 , H03C3/09 , H04L27/20
CPC分类号： H03C3/0966 , H03C3/08 , H03C3/0941 , H03C3/095 , H03B28/00 , H03C2200/005 , H03C2200/0079
摘要： The present invention, generally speaking, provides an RF modulator that allows precise, stable phase shifts to be obtained. The modulator uses a PLL structure including an auxiliary feedforward path used to inject a baseband modulation signal into the PLL at a point past a loop filter of the PLL. A phase demodulator recovers phase information from the output signal of the PLL. The recovered phase information is compared to the phase information of the baseband modulation signal. A resulting error signal is used to control injection of the baseband modulation signal into the PLL, to automatically achieve the correct "dosage." A precise, adaptive, phase-stable modulator results. The adaptation of the modulator compensates for variability of the VCO and other components of the PLL.
摘要翻译：本发明一般地提供了一种能够获得精确，稳定的相移的RF调制器。调制器使用PLL结构，其包括用于在通过PLL的环路滤波器的点将基带调制信号注入到PLL中的辅助前馈路径。相位解调器从PLL的输出信号中恢复相位信息。将恢复的相位信息与基带调制信号的相位信息进行比较。所产生的误差信号用于控制基带调制信号的注入到PLL中，以自动实现正确的“剂量”。一个精确的，自适应的相位稳定调制器。调制器的调整补偿了VCO和PLL的其他组件的变化。

45. 发明授权

US5844388A Drive systems for a brushless motor employing predefined driving profiles stored in a nonvolatile memory 失效
标题翻译：用于无刷电机的驱动系统，其采用存储在非易失性存储器中的预定义的驱动简档
公开(公告)号：US5844388A
公开(公告)日：1998-12-01
申请号：US828167
申请日：1997-03-18
申请人： Giuseppe Maiocchi
发明人： Giuseppe Maiocchi
IPC分类号： H02P6/10 , H02P6/34 , H02P23/00 , H03B28/00 , H03L7/06
CPC分类号： H02P6/10 , H02P23/0077 , H02P6/34 , Y10S388/904
摘要： The torque characteristic of an electrically driven brushless motor may be optimized by driving the phase windings of the motor with predefined, digitized and stored current or voltage profiles. Appropriate sequences of digital samples of the predefined driving profile are sequentially read from a nonvolatile memory where they are permanently stored to drive, through a DAC, the relative winding of the motor in synchronism with a signal representative of the rotor position.
摘要翻译：可以通过用预定义的，数字化和存储的电流或电压曲线来驱动电动机的相绕组来优化电驱动的无刷电动机的转矩特性。从非易失性存储器中顺序地读取预定义驱动简档的数字样本的适当序列，其中它们被永久存储，以通过DAC与代表转子位置的信号同步地驱动马达的相对绕组。

46. 发明授权

US5815045A Oscillation apparatus 失效
标题翻译：振荡装置
公开(公告)号：US5815045A
公开(公告)日：1998-09-29
申请号：US645752
申请日：1996-05-14
申请人： Miyuki Koyanagi , Takeo Yasukawa , Koichi Murakami
发明人： Miyuki Koyanagi , Takeo Yasukawa , Koichi Murakami
IPC分类号： H03B11/00 , H03B28/00 , H03B29/00 , H03L7/08
CPC分类号： H03B28/00
摘要： An oscillation apparatus is provided with a present value generating unit for generating a present value which is monotonously increased or decreased with the passage of time; a threshold value generating unit for generating a threshold of which a value is periodically varied; a comparing and detecting unit for comparing the present value generated in said present value generating unit with the threshold generated in said threshold value generating unit; a present value reset unit for resetting the present value to a predetermined initial value whenever said comparing and detecting unit detects a fact that the present value reached the threshold; and a signal generating unit for generating sequentially signals of which a period is defined by a time interval of timing-to-timing in which said comparing and detecting detects a fact that the present value reached the threshold.
摘要翻译：振荡装置具有产生随时间而单调增减的现值的现值生成部，阈值生成单元，用于生成周期性变化的值的阈值; 比较和检测单元，用于将在所述当前值生成单元中生成的当前值与在所述阈值生成单元中生成的阈值进行比较; 每当所述比较和检测单元检测到所述当前值达到所述阈值的事实时，将所述当前值重置为预定初始值的当前值复位单元; 信号产生单元，用于根据所述比较和检测的时间间隔来检测出当前值达到阈值的事实，顺序地生成周期定义的信号。

47. 发明授权

US5801654A Apparatus and method for frequency translation in a communication device 失效
标题翻译：通信设备中频率转换的装置和方法
公开(公告)号：US5801654A
公开(公告)日：1998-09-01
申请号：US407546
申请日：1995-03-20
申请人： Kevin Bruce Traylor
发明人： Kevin Bruce Traylor
IPC分类号： H03M1/74 , G06J1/00 , H03B28/00 , H03D7/00 , H03D7/16 , H04B1/16 , H03M1/64
CPC分类号： G06J1/00 , H03D7/00 , H03D2200/005 , H03D2200/0052 , H03D2200/0068 , H03D2200/007 , H03D2200/0072 , H03D7/165
摘要： A frequency translation device in a first embodiment includes a plurality of multiplying digital-to-analog converters (MDACs) that multiply an input signal by phase shifted digital sinewave approximation signals to perform frequency translation. In the preferred embodiment the input includes inphase and quadrature phase components, one of which is multiplied by a digital sinewave approximation and the other is multiplied by a digital cosinewave approximation. The use of the multiple MDACs with differing sinewave approximation signals provides a signal that multiplies the input signal such that the effects of odd harmonics at an output are mitigated while the advantages of a traditional switching mixer are retained.
摘要翻译：第一实施例中的频率转换装置包括多个乘法数模转换器（MDAC），其通过相移数字正弦波近似信号将输入信号相乘以执行频率转换。在优选实施例中，输入包括同相和正交相分量，其中一个相乘与数字正弦波近似，另一个乘以数字余弦波近似。使用具有不同正弦波近似信号的多个MDAC提供了将输入信号相乘的信号，使得输出端的奇次谐波的效果得到缓解，同时传统的开关混频器的优点得以保留。

48. 发明授权

US5801589A Frequency synthesizer which suppresses a spurious 失效
标题翻译：频率合成器抑制杂散
公开(公告)号：US5801589A
公开(公告)日：1998-09-01
申请号：US781519
申请日：1997-01-09
申请人： Kenichi Tajima , Kenji Itoh , Shuji Nishimura , Masayuki Doi , Akio Iida
发明人： Kenichi Tajima , Kenji Itoh , Shuji Nishimura , Masayuki Doi , Akio Iida
IPC分类号： H03B28/00 , H03L7/18 , H03L7/183 , H03L7/00 , H03B27/00
CPC分类号： H03L7/1806
摘要： A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.
摘要翻译：在基准振荡器中设置有可以设定分频数设定参数的可变分频器。当选择频率设定参数时，响应于来自PLL的输出频率，DDS将不会以PLL的输出频带内的指定电平或高于指定电平的电平输出杂散，转换功能对PLL中的可变分频器的设定参数和参考振荡器中的可变分频器的分频数设定参数进行调整，使得输出频率和所选择的频率设定参数得到满足。

49. 发明授权

US5760617A Voltage-to-frequency converter 失效
标题翻译：电压 - 频率转换器
公开(公告)号：US5760617A
公开(公告)日：1998-06-02
申请号：US700288
申请日：1996-08-20
申请人： Michael C. Coln , Eric Nestler
发明人： Michael C. Coln , Eric Nestler
IPC分类号： H03B28/00 , H03C3/00 , H03M1/86 , H03G3/06
CPC分类号： H03C3/00 , H03M1/86 , H03B28/00
摘要： A voltage-to-frequency converter having an analog-to-digital converter, based on analog components, for converting samples of an analog signal into corresponding digital words and a digital-to-frequency converter, based on digital components, for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog signal. With such an arrangement, the digital-to-frequency converter and the analog-to-digital converter are adapted to operate at different rates. Therefore, the analog-to-digital converter may be optimized at one operating rate while the digital-to-frequency converter is adapted to operate at a higher operating rate and over a wide range of operating rates. This arrangement thereby enables a slower, analog component based, analog-to-digital converter to be used fabricated with CMOS technology along with the higher, variable operating rate, digital component based, digital-to-frequency converter. The digital-to-frequency converter includes a register and an adder for summing the digital words with contents stored in the register to produce a sum thereof. The sum is stored in the register. An interpolator is provided between the analog-to-digital converter and the digital-to-frequency converter for providing digital words for the digital-to-frequency converter at a rate greater than the operating rate of the analog-to-digital converter.
摘要翻译：一种具有基于模拟部件的模拟数字转换器的电压 - 频率转换器，用于将模拟信号的样本转换成相应的数字字，并且基于数字部件将数字 - 频率转换器转换成用于将数字将单词转换成具有与模拟信号相关的脉冲重复频率的脉冲序列。通过这样的布置，数字 - 频率转换器和模 - 数转换器适于以不同的速率进行操作。因此，可以在一个工作速率下优化模数转换器，同时数字 - 频率转换器适于以较高的工作速率和较宽的工作速率范围工作。因此，这种布置使得能够使用用CMOS技术制造的较慢的基于模拟分量的模数转换器以及较高可变工作速率的基于数字分量的数 - 频转换器。数字 - 频率转换器包括寄存器和加法器，用于将数字字与存储在寄存器中的内容相加以产生它们的和。总和存储在寄存器中。在模数转换器和数 - 频转换器之间提供一个内插器，用于以大于模 - 数转换器工作速率的速率为数 - 频转换器提供数字字。

50. 发明授权

US5754597A Method and apparatus for routing a digitized RF signal to a plurality of paths 失效
标题翻译：用于将数字化RF信号路由到多个路径的方法和装置
公开(公告)号：US5754597A
公开(公告)日：1998-05-19
申请号：US619229
申请日：1996-03-21
申请人： Daniel M. Lurey , Yuda Y. Luz , Sheila M. Rader , Alan P. Rottinghaus
发明人： Daniel M. Lurey , Yuda Y. Luz , Sheila M. Rader , Alan P. Rottinghaus
IPC分类号： H03D7/00 , H01Q1/24 , H01Q3/26 , H03B28/00 , H03C1/00 , H03C3/00 , H03D7/16 , H04B1/04 , H04B1/16 , H04B1/26 , H04B1/28 , H04B1/38 , H04B1/40 , H04B7/04 , H04B7/06 , H04B7/08 , H04B7/185 , H04B7/24 , H04B7/26 , H04L1/06 , H04L1/22 , H04L27/20 , H04W4/18 , H04W88/06 , H04L27/04
CPC分类号： H01Q1/246 , H01Q3/2605 , H03C1/00 , H03C3/00 , H03D7/165 , H04B1/0003 , H04B1/001 , H04B1/0017 , H04B1/0021 , H04B1/0483 , H04B1/16 , H04B1/26 , H04B1/28 , H04B1/38 , H04B1/40 , H04B7/04 , H04B7/0691 , H04B7/0802 , H04B7/18515 , H04B7/24 , H04L1/06 , H04L1/22 , H03B28/00 , H04B7/06 , H04B7/0874 , H04W4/18 , H04W88/06
摘要： Generally stated, an apparatus and method for routing a digitized radio frequency (RF) signal 140-143 to a plurality of paths is described herein. In accordance with a first preferred embodiment, the apparatus comprises a digital upconverter/modulator (DUC) 125, 129 coupled to a scaling and switching network 100N which is comprised of, at minimum, a first, second, third and fourth digital switch, and a first, second and third adder. Within the scaling and switching network 100N, the first digital switch is responsive to the DUC 125,129. The first adder is responsive to the first and second digital switches, while the second adder is responsive to the third and fourth digital switches. Finally, the third adder is responsive to the first and second adders.
摘要翻译：一般来说，这里描述了用于将数字化射频（RF）信号140-143路由到多个路径的装置和方法。根据第一优选实施例，该装置包括耦合到缩放和交换网络100N的数字上变频器/调制器（129），其至少包括第一，第二，第三和第四数字开关，以及第一，第二和第三加法器。在缩放和交换网络100N内，第一数字开关响应于DUC 125,129。第一加法器响应于第一和第二数字开关，而第二加法器响应于第三和第四数字开关。最后，第三加法器响应于第一和第二加法器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式