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41. 发明授权

US06828820B2 Method and circuit for producing control signal for impedance matching 有权
公开(公告)号：US06828820B2
公开(公告)日：2004-12-07
申请号：US10435112
申请日：2003-05-08
申请人： Tsuyoshi Ohno
发明人： Tsuyoshi Ohno
IPC分类号： H03K19003
CPC分类号： H03K19/0005 , H04L25/0278
摘要： A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.

42. 发明授权

US06809547B2 Multi-function interface and applications thereof 有权
标题翻译：多功能接口及其应用
公开(公告)号：US06809547B2
公开(公告)日：2004-10-26
申请号：US10305648
申请日：2002-11-27
申请人： Joseph Ingino , Vincent Von Kaenel
发明人： Joseph Ingino , Vincent Von Kaenel
IPC分类号： H03K19003
CPC分类号： H03K19/018571 , G06F13/4072 , H04L25/0278 , H04L25/028
摘要： A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.

43. 发明授权

US06798236B2 Output buffer circuit with power supply voltages different from a power supply voltage applied to an internal circuit 失效
标题翻译：输出缓冲电路，其电源电压不同于施加到内部电路的电源电压
公开(公告)号：US06798236B2
公开(公告)日：2004-09-28
申请号：US10271799
申请日：2002-10-17
申请人： Tadayuki Shimizu , Takafumi Takatsuka , Masaki Tsukude
发明人： Tadayuki Shimizu , Takafumi Takatsuka , Masaki Tsukude
IPC分类号： H03K19003
CPC分类号： H03K19/0016 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.
摘要翻译：一种半导体集成电路，其从外部提供第一电源电压和第二电源电压，以便操作并入的电路，并且在输出端子处输出数据，包括执行用于输入信号的预定功能的内部电路输出电路，其包括用于将来自内部电路的信号转换为输出信号的第一电路和包含最终级缓冲电路的第二电路，其根据来自第一电路的信号将数据输出到输出端; 以及将提供给第二电路的电源电压切换到第一电源电压或第二电源电压的开关电路。通过减小第一电源电压获得的电压被提供给内部电路。第一电源电压被提供给第一电路。

44. 发明授权

US06794900B2 Method and circuit for pre-emphasis equalization in high speed data communications 有权
标题翻译：高速数据通信中预加重均衡的方法和电路
公开(公告)号：US06794900B2
公开(公告)日：2004-09-21
申请号：US10205340
申请日：2002-07-24
申请人： Benjamim Tang , Richard C. Pierson
发明人： Benjamim Tang , Richard C. Pierson
IPC分类号： H03K19003
CPC分类号： H04L25/0286 , H04L25/0272 , H04L25/0288 , H04L25/03878
摘要： A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude. The amount of amplitude change from full scale back to mid-scale determines the amount of equalization to be provided by the output buffer to the transmission channel.
摘要翻译：可以通过使用可编程脉冲整形来提供用于高速数据通信系统的预加重均衡的方法和电路。配置有预加重均衡电路的数据通信系统通过接收输入数据流并通过互连或其他传输信道输出数据流进行传输。数据可以通过配置有可编程预加重均衡的输出缓冲器，在输入级具有输入反相器，并在输出级输出反相器。在操作期间，一旦输入级的输入信号转变，例如从低电平到高电平状态，到输出级的输入信号被配置为全幅度以驱动传输通道。一旦输出级转变到一个完整的幅度，输出级的输入被配置成更接近中等幅度。从满量程到中等刻度的幅度变化量决定了输出缓冲器向传输通道提供的均衡量。

45. 发明授权

US06794895B2 Power saving termination technique for differential signaling 失效
公开(公告)号：US06794895B2
公开(公告)日：2004-09-21
申请号：US10186005
申请日：2002-06-27
申请人： Maynard C. Falconer
发明人： Maynard C. Falconer
IPC分类号： H03K19003
CPC分类号： H04L25/0298
摘要： A technique for reducing power consumption in voltage and current steered differential busses that transmit and receive encoded signals is described. A circuit is used to save power in the static state. The circuit blocks static current flow, but allows the frequency components associated with the signaling band.

46. 发明授权

US06791361B2 Technique for mitigating gate leakage during a sleep state 失效
标题翻译：在睡眠状态下减轻门漏电的技术
公开(公告)号：US06791361B2
公开(公告)日：2004-09-14
申请号：US10319002
申请日：2002-12-12
申请人： Elad Alon , Jeffrey L. Burns , Kevin J. Nowka , Rahul M. Rao
发明人： Elad Alon , Jeffrey L. Burns , Kevin J. Nowka , Rahul M. Rao
IPC分类号： H03K19003
CPC分类号： H03K19/0016
摘要： A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.
摘要翻译：一种在睡眠状态下减轻门漏电的方法和电路。在休眠状态期间，可以将输入模式应用于电路中的多个设备中的一个或多个，例如静态电路，动态电路。响应于输入图案的应用，电路中的大多数器件可以在其每个端子，即源极，栅极和漏极端子处具有基本相同的电压，从而减轻栅极泄漏。

47. 发明授权

US06788101B1 Programmable interface circuit for differential and single-ended signals 有权
公开(公告)号：US06788101B1
公开(公告)日：2004-09-07
申请号：US10366956
申请日：2003-02-13
申请人： Arifur Rahman
发明人： Arifur Rahman
IPC分类号： H03K19003
CPC分类号： H04L25/0276 , H03K19/017581 , H04L25/028 , H04L25/0292
摘要： A programmable interface circuit is disclosed, in accordance with one embodiment, which supports differential and single-ended signaling. For example, an input buffer within the programmable interface circuit is configurable to receive differential signals or single-ended signals. A multiplexer provides the appropriate reference signal to the input buffer, when configured to receive single-ended signals, by selecting the reference signal from a plurality of reference buses. The multiplexer, along with a capacitor, may also provide lowpass filtering of the reference signal. Furthermore, an output buffer may be configurable utilizing techniques similar to that described for the input buffer.

48. 发明授权

US06768334B1 Signal transmitting receiving apparatus 有权
标题翻译：信号发送接收装置
公开(公告)号：US06768334B1
公开(公告)日：2004-07-27
申请号：US09553308
申请日：2000-04-20
申请人： Hiroyuki Yamauchi , Tadahiro Yoshida
发明人： Hiroyuki Yamauchi , Tadahiro Yoshida
IPC分类号： H03K19003
CPC分类号： H01P5/02
摘要： A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data lines and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
摘要翻译：根据本发明的信号发送/接收装置包括：发送装置，用于发送数据; 用于接收数据的接收装置; 用于发送数据的数据线; 以及用于发送用于确定数据线的电压的偏置电压的电源线，其中所述发送装置和所述接收装置通过所述数据线和所述供给线彼此连接，所述发送装置包括：驱动器电路，用于输出数据线路的数据和偏置产生装置，用于产生偏置电压并将偏置电压输出到电源线，所述接收装置包括：连接到数据线的终端电阻; 以及用于检测来自数据线的数据的接收器电路，其中数据线经由终端电阻器连接到电源线。

49. 发明授权

US06762617B2 Semiconductor device having test mode entry circuit 有权
标题翻译：具有测试模式进入电路的半导体器件
公开(公告)号：US06762617B2
公开(公告)日：2004-07-13
申请号：US10321460
申请日：2002-12-18
申请人： Akihiro Iwase , Yoshiharu Kato
发明人： Akihiro Iwase , Yoshiharu Kato
IPC分类号： H03K19003
CPC分类号： G11C29/40 , G01R31/31701 , G11C11/40 , G11C29/1201 , G11C29/46 , G11C2029/0407
摘要： A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.
摘要翻译：半导体器件具有正常工作模式和测试模式。决定电路确定设备是否进入测试模式。当输入测试模式时，控制电路改变与正常操作模式有关的信息。如果意外输入测试模式，则由于与正常操作有关的信息已经改变，用户可以容易地确定设备已进入测试模式。

50. 发明授权

US06756812B2 Differential termination resistor adjusting circuit 失效
标题翻译：差分终端电阻调节电路
公开(公告)号：US06756812B2
公开(公告)日：2004-06-29
申请号：US10263661
申请日：2002-10-04
申请人： Hideo Nagano , Takahiro Miki
发明人： Hideo Nagano , Takahiro Miki
IPC分类号： H03K19003
CPC分类号： H04L25/0298
摘要： A differential termination resistor adjusting circuit includes: a reference current producing section that produces a nearly constant reference current Iref, a reference voltage producing section that produces nearly constant reference voltages VrefH, VrefL, a replica resistor producing section that is provided with the reference current Iref to produce voltage drops Va, Vb, a control voltage producing section that produces control voltages Vcont1, Vcont2, based on the reference voltages VrefH, VrefL and the voltage drops Va, Vb, and a genuine resistor producing section that is built in a receiving side device and is connected to an input termination, characterized in that the resistances of the replica resistor producing section and the genuine resistor producing section are adjusted by the control voltages Vcont1, Vcont2.
摘要翻译：差分终端电阻调节电路包括：产生几乎恒定的参考电流Iref的参考电流产生部分，产生几乎恒定的参考电压VrefH，VrefL的参考电压产生部分，具有参考电流I ref的复制电阻产生部分产生电压降Va，Vb，基于参考电压VrefH，VrefL和电压降Va，Vb产生控制电压Vcont1，Vcont2的控制电压产生部分和内置在接收侧的正电阻产生部分并且连接到输入端子，其特征在于，通过控制电压Vcont1，Vcont2调节复制电阻产生部分和正电阻产生部分的电阻。

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