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41. 发明授权

US5224065A Arithmetic operation unit having bit inversion function 失效
标题翻译：具有位反转功能的算术运算单元
公开(公告)号：US5224065A
公开(公告)日：1993-06-29
申请号：US814719
申请日：1991-12-30
申请人： Makoto Yoshida
发明人： Makoto Yoshida
IPC分类号： G06F7/501 , G06F7/50 , G06F7/503 , G06F7/506 , G06F7/575
CPC分类号： G06F7/503 , G06F7/575 , G06F2207/3852
摘要： A bit-inversion arithmetic operation unit comprises a first carry signal line for propagating a carry signal from a more significant bit position side to a less significant bit position side, and a second carry signal line for propagating a carry signal from a less significant bit position side to a more significant bit position side. A common logic circuit performs at least a portion of a carry control including a carry propagation of the first and second carry signals and a carry generation. A switching and logic circuit responds to a required arithmetic operation mode so as to control the common logic circuit and to perform the remaining portion of the carry control including the carry propagation of the first and second carry signals and the carry generation.

42. 发明授权

US5206940A Address control and generating system for digital signal-processor 失效
标题翻译：数字信号处理器的地址控制和发生系统
公开(公告)号：US5206940A
公开(公告)日：1993-04-27
申请号：US750512
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译：一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线，地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元执行阶段

43. 发明授权

US4888722A Parallel arithmetic-logic unit for as an element of digital signal processor 失效
标题翻译：用作数字信号处理器元件的并行算术逻辑单元
公开(公告)号：US4888722A
公开(公告)日：1989-12-19
申请号：US69431
申请日：1987-07-02
申请人： Charles P. Boreland
发明人： Charles P. Boreland
IPC分类号： G06F7/575
CPC分类号： G06F7/575
摘要： A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.

44. 发明授权

US4815019A Fast ALU equals zero circuit 失效
标题翻译：快速ALU等于零电路
公开(公告)号：US4815019A
公开(公告)日：1989-03-21
申请号：US19101
申请日：1987-02-26
申请人： Patrick W. Bosshart
发明人： Patrick W. Bosshart
IPC分类号： G06F7/02 , G06F7/575 , G06F7/38
CPC分类号： G06F7/575 , G06F7/02
摘要： A fast ALU=0 circuit is used with a carry-select lookahead ALU. Preliminary ALU=0 signals are derived for each section of the ALU prior to a carry in signal being received by that section. When the carry in signal is received, a final comparison is made with the least significant bit of the section and the final ALU=0 signal generated. The ALU=0 computation is complete one gate delay after the ALU computation is complete.
摘要翻译：快速ALU = 0电路与进位选择前视图ALU一起使用。在由该部分接收到进位信号之前，对ALU的每个部分导出初步ALU = 0信号。当接收到进位信号时，最后比较该部分的最低有效位，并产生最终的ALU = 0信号。在ALU计算完成之后，ALU = 0计算完成一个门延迟。

45. 发明授权

US4810995A Arithmetic and logic operating unit 失效
标题翻译：算术逻辑运算单元
公开(公告)号：US4810995A
公开(公告)日：1989-03-07
申请号：US21666
申请日：1987-02-09
申请人： Harufusa Kondou , Hideki Ando
发明人： Harufusa Kondou , Hideki Ando
IPC分类号： G06F7/02 , G06F7/38 , G06F7/508 , G06F7/575 , H03M1/34 , H03M5/18
CPC分类号： G06F7/575 , H03M5/18 , G06F7/49921
摘要： An arithmetic and logic unit control circuit includes arithmetic circuits (10a-10d) for generating the absolute value .vertline.A.vertline. of an input signal A and the complement B of an input signal B from n-bit input signals A and B in response to a control signal from a controller (14). Full adders (6a-6d) add outputs from the arithmetic circuits in response to a control signal from the controller (14). First logic circuits (20a-20c, 21) extract the most significant bit of (.vertline.A.vertline.-B) to form outputs of the full adders (6a-6d) in response to a control signal from controller (14) and second logic circuits (20e, 21) to perform a three-level decision of values A and B from the outputs of the first logic circuits (20a-20c, 21) and the most significant bit of the input signal A. The arithmetic and logic unit can thereby perform Alternate Mark Inversion (AMI) coding in one machine cycle.
摘要翻译：算术和逻辑单元控制电路包括用于根据来自n位输入信号A和B的输入信号A的输入信号B的绝对值| A |和输入信号B的补码和上升＆amp; B的运算电路（10a-10d）响应于来自控制器（14）的控制信号。响应于来自控制器（14）的控制信号，全加器（6a-6d）从运算电路添加输出。响应于来自控制器（14）和第二逻辑电路（14）的控制信号，第一逻辑电路（20a-20c，21）提取（| A|-B）的最高有效位以形成全加器（6a-6d）的输出（20e，21）从第一逻辑电路（20a-20c，21）的输出和输入信号A的最高有效位执行值A和B的三电平判定。由此算术和逻辑单元在一个机器周期中执行替代标记反转（AMI）编码。

46. 发明授权

US4706209A Arithmetic and logic unit with overflow indicator 失效
标题翻译：具有溢出指示器的算术逻辑单元
公开(公告)号：US4706209A
公开(公告)日：1987-11-10
申请号：US696910
申请日：1985-01-31
申请人： Andre Picco
发明人： Andre Picco
IPC分类号： G06F7/38 , G06F7/00 , G06F7/499 , G06F7/575 , G06F7/50
CPC分类号： G06F7/575 , G06F7/4991
摘要： The invention concerns the overflow test circuit of an arithmetic and logic unit. The circuit described does not require receiving an indication on the operating in addition or subtraction of the ALU; it receives simply the carrying input the carrying and the result output of the cell of the highest rank of the ALU: and it supplies a positive overflow signal or a negative overflow signal, when the result of the addition or subtraction of two numbers exceeds the capacity of the ALU. Two gates with three inputs and three inverters are sufficient to establish the overflow test circuit.
摘要翻译：本发明涉及算术和逻辑单元的溢出测试电路。所描述的电路不需要接收关于ALU的加法或减法的操作的指示; 它只接收携带输入的ALU的最高级别的单元的携带和结果输出，并且当两个数字的相加或减去的结果超过容量时，它提供正的溢出信号或负的溢出信号的ALU。具有三个输入和三个反相器的两个门足以建立溢出测试电路。

47. 发明授权

US4644489A Multi-format binary coded decimal processor with selective output formatting 失效
标题翻译：具有选择性输出格式的多格式二进制编码十进制处理器
公开(公告)号：US4644489A
公开(公告)日：1987-02-17
申请号：US579091
申请日：1984-02-10
申请人： Richard R. Curtin , Paul M. Clemente
发明人： Richard R. Curtin , Paul M. Clemente
IPC分类号： G06F7/38 , G06F5/00 , G06F7/00 , G06F7/48 , G06F7/491 , G06F7/493 , G06F7/575
CPC分类号： G06F7/491 , G06F7/575
摘要： Digital circuitry performs arithmetic operations upon first and second binary coded decimal digit strings input thereto. The digital circuitry provides for receiving and storing a first and second BCD digit, the digits having an arbitrary data type format. The first and second data types are selected from the group of packed and unpacked data. The circuitry then performs the arithmetic operation upon the stored BCD digits to obtain a result data word which is made available in a data type format corresponding to a selected one of the input BCD digits. In a particular embodiment, a plurality of the circuits can be operated in a digit slice structure. The digit slice structure operates upon strings of packed, unpacked, and mixed data type arithmetic operands and provides, at its output lines, output data in a format corresponding to a selected input data type. In particular, a unique interconnection of the plural output lines of the circuitry enables the output data type to be packed or unpacked as desired. The circuitry also provides for automatic selection of digits applied to the circuitry thereby relieving the operating environment from significant time consuming and costly supervision.
摘要翻译：数字电路对输入到其的第一和第二二进制编码十进制数字串进行算术运算。数字电路提供接收和存储第一和第二BCD数字，这些数字具有任意的数据类型格式。第一和第二数据类型是从打包和解压缩数据组中选择的。然后，电路对所存储的BCD数字执行算术运算，以获得结果数据字，该结果数据字以对应于输入BCD数字中所选择的一个的数据类型格式可用。在特定实施例中，多个电路可以以数字切片结构操作。数字切片结构对打包的，未打包的和混合的数据类型的算术运算符的串进行操作，并且在其输出行提供与所选择的输入数据类型对应的格式的输出数据。特别地，电路的多个输出线的独特互连使得输出数据类型能够根据需要被打包或解包。电路还提供自动选择应用于电路的数字，从而减轻操作环境的耗时和昂贵的监督。

48. 发明授权

US4435782A Data processing system with high density arithmetic and logic unit 失效
标题翻译：具有高密度算术和逻辑单元的数据处理系统
公开(公告)号：US4435782A
公开(公告)日：1984-03-06
申请号：US278794
申请日：1981-06-29
申请人： Dan R. Kaufman , Gerhard R. Thompson
发明人： Dan R. Kaufman , Gerhard R. Thompson
IPC分类号： G06F7/00 , G06F7/501 , G06F7/503 , G06F7/575 , H03K19/20 , H03K19/21 , G06F7/48 , G06F7/50
CPC分类号： G06F7/575 , G06F2207/3896
摘要： A multi-stage, multi-function, arithmetic and logic unit for a data processing system is formed with only a small number of components. Some of the functions (Sum and Exclusive OR) are performed within each stage. For other functions (AND and OR), some of the components of one stage cooperate with different components of the next stage in an arrangement that reduces the total number of components for each stage. For these functions, the output appears shifted one bit position to the left and is then re-shifted one bit position to the right by a conventionally available shifter.
摘要翻译：用于数据处理系统的多级，多功能，算术和逻辑单元仅由少量组件形成。在每个阶段都执行一些功能（Sum和Exclusive OR）。对于其他功能（AND和OR），一个阶段的一些组件与下一阶段的不同组件配合，可以减少每个阶段的组件总数。对于这些功能，输出出现向左移位一位位置，然后通过常规可用的移位器向右移位一位位置。

49. 发明授权

US4160290A One-bit multifunction arithmetic and logic circuit 失效
标题翻译：一位多功能算术和逻辑电路
公开(公告)号：US4160290A
公开(公告)日：1979-07-03
申请号：US894795
申请日：1978-04-10
申请人： Rolfe D. Armstrong
发明人： Rolfe D. Armstrong
IPC分类号： G06F7/00 , G06F7/50 , G06F7/501 , G06F7/575 , H03K19/08
CPC分类号： G06F7/501 , G06F7/575 , G06F2207/3896
摘要： A one bit multifunction arithmetic and logic circuit is implemented with a pair of inverters, four two input NOR gates, three two-input OR/NOR gates, and two three-input NOR gates. Each of the inverters has four wire OR-able outputs, two of which are inverting and two of which are non-inverting. One input of each of the four two-input NOR gates is coupled to a respective one of four control inputs of the arithmetic and logic circuit; the other input thereof is coupled to respective ones of four wire ORed combinations of the outputs of the first and second inverters. Various outputs of the first, second, third, and fourth two-input NOR gates are wire ORed together. A first one of the three-input NOR gates is responsive to the generate signal, a carry signal, and the wired OR output of the first and second two-input NOR gates. The second three-input NOR gate is responsive to the propagate signal, a carry signal, and the "output disable" input. The first outputs of the first and second three-input NOR gates are wire ORed together to produce a first "sum" output; the second output of the first and second three-input NOR gates are wire ORed together to produce a second sum output which may be used as a wire OR-able "zero result" indicator signal.

50. 发明授权

US4139894A Multi-digit arithmetic logic circuit for fast parallel execution 失效
标题翻译：用于快速并行执行的多位算术逻辑电路
公开(公告)号：US4139894A
公开(公告)日：1979-02-13
申请号：US769414
申请日：1977-02-17
申请人： Jogchum Reitsma
发明人： Jogchum Reitsma
IPC分类号： G06F7/493 , G06F7/494 , G06F7/50 , G06F7/507 , G06F7/575
CPC分类号： G06F7/494 , G06F7/507 , G06F7/575 , G06F2207/3876 , G06F2207/4924
摘要： A simple and fast arithmetic member for multi-digit numbers. For each digit a module is provided which receives the digits of corresponding significance and which first forms two output carry signals therefrom, i.e. one as if the relevant module always receives an input carry signal (E) and one as if this module never receives an input carry signal (D). Between successive modules each time functionally identical configurations of logic elements are connected which, under the control of the input carry signal to the module (Ci) of next-lower significance, the two output carry signals (Di, Ei) thereof, and an enable signal, forms the input carry signal for the stage of next-higher significance (C(i+1)) in accordance with the formulaC (i + 1) = Di + Ei.multidot.Ci.
摘要翻译：一个简单而快速的算术成员，用于多位数字。对于每个数字，提供接收相应重要性的数字的模块，并且其首先形成两个输出进位信号，即，如同相关模块总是接收输入进位信号（E）一样，并且一个如同该模块从未接收到输入进位信号（D）。在连续的模块之间，每次连接功能相同的逻辑元件配置时，在输入进位信号的控制下连接到下一个有效位的模块（Ci），其两个输出进位信号（Di，Ei）和一个使能信号，根据公式C（i + 1）= Di + EixCi，形成下一更高有效级（C（i + 1））阶段的输入进位信号。

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