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41. 发明申请

US20150027757A1 PCB HAVING GLASS CORE 审中-公开
标题翻译： PCB玻璃芯
公开(公告)号：US20150027757A1
公开(公告)日：2015-01-29
申请号：US14074372
申请日：2013-11-07
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Yee Na SHIN , Seung Eun Lee
IPC分类号： H05K1/03 , H05K1/02
CPC分类号： H05K3/4605 , H01L23/15 , H01L23/49827 , H01L23/50 , H01L2924/0002 , H05K1/0271 , H05K1/185 , H05K3/107 , H05K3/426 , H05K3/4661 , H05K2201/0376 , H05K2201/098 , H01L2924/00
摘要： Disclosed herein is a printed circuit board (PCB) including a glass core for maintaining sufficient rigidity while maintaining a thin thickness to minimize warpage. The PCB includes a glass core having upper and lower surfaces in which pattern formation grooves and through via holes are formed, a plating layer filled in the pattern formation groves and the through via holes, insulating layers stacked on the upper and lower surfaces of the glass core, and solder resist layers formed on the insulating layers via coating.
摘要翻译：本文公开了一种印刷电路板（PCB），其包括玻璃芯，用于保持足够的刚度，同时保持薄的厚度以使翘曲最小化。 PCB包括具有上表面和下表面的玻璃芯，其中形成图案形成沟槽和穿过通孔，填充在图案形成沟槽中的镀层和穿通通孔，堆叠在玻璃的上表面和下表面上的绝缘层芯和阻焊层，通过涂层形成在绝缘层上。

42. 发明申请

US20140353019A1 FORMATION OF DIELECTRIC WITH SMOOTH SURFACE 审中-公开
标题翻译：用平滑表面形成电介质
公开(公告)号：US20140353019A1
公开(公告)日：2014-12-04
申请号：US13906229
申请日：2013-05-30
申请人： Deepak Arora , Daniel N. Sobieski , Dilan Seneviratne , Ebrahim Andideh , James C. Meyer
发明人： Deepak Arora , Daniel N. Sobieski , Dilan Seneviratne , Ebrahim Andideh , James C. Meyer
IPC分类号： C23C14/22 , H05K1/11 , H01L21/02 , H05K1/03 , C23C14/34 , C23C14/14
CPC分类号： H05K3/4644 , B32B38/10 , B32B43/006 , C23C14/228 , H01L21/44 , H01L21/48 , H01L21/565 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H05K3/0014 , H05K3/0035 , H05K3/0044 , H05K3/0055 , H05K3/107 , H05K3/281 , H05K3/42 , H05K2203/0554 , H05K2203/1105 , H05K2203/1152 , Y10T156/1168 , Y10T156/1978
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及用于形成具有光滑表面的电介质的技术和配置。在一个实施例中，一种方法包括提供具有第一表面和第二表面的电介质，形成在第一表面上的导电特征，以及施加到第二表面的层压板，在层压体保持施加时固化第二表面，以及去除层压体。可以描述和/或要求保护其他实施例。

43. 发明申请

US20140353009A1 TRANSPARENT CONDUCTIVE FILM 有权
标题翻译：透明导电膜
公开(公告)号：US20140353009A1
公开(公告)日：2014-12-04
申请号：US13975276
申请日：2013-08-23
申请人： NANCHANG O-FILM TECH CO., LTD. , SHENZHEN O-FILM TECH CO., LTD. , SUZHOU O-FILM TECH CO., LTD.
发明人： YUNHUA ZHAO , YULONG GAO , YUNLIANG YANG , YING GU
IPC分类号： H05K1/03 , H05K1/02
CPC分类号： H05K3/361 , G06F3/044 , G06F2203/04103 , H05K1/0228 , H05K1/036 , H05K1/0393 , H05K3/107 , H05K3/1258 , H05K2201/0108 , H05K2201/0129 , H05K2201/053 , H05K2201/09036 , H05K2201/09681 , H05K2201/09827 , H05K2203/1572
摘要： A transparent conductive film, includes: a transparent substrate, wherein a transparent substrate includes a body and a flexible board, a width of flexible board is less than that of the body, and the body includes a sensing area and a border area located at an edge of the sensing area; a conduction line, disposed on a transparent flexible substrate; a first conductive layer and a second conductive layer, disposed on two sides of the sensing area opposite to each other; a first electrode trace and a second electrode trace, disposed on the border area, and the first conductive layer and the conduction line are electrically connected through a first electrode trace; the second conductive layer and the conduction line are electrically connected through a second electrode trace. The production efficiency of the above transparent conductive film is improved.
摘要翻译：一种透明导电膜，包括：透明基板，其中透明基板包括主体和柔性板，柔性板的宽度小于主体的宽度，并且主体包括感测区域和位于传感区域的边缘; 导线，设置在透明柔性基板上; 第一导电层和第二导电层，设置在彼此相对的感测区域的两侧; 设置在边界区域上的第一电极迹线和第二电极迹线以及第一导电层和导电线通过第一电极迹线电连接; 第二导电层和导线通过第二电极迹线电连接。上述透明导电膜的制造效率提高。

44. 发明授权

US08894892B2 Mold and manufacturing method therefor 有权
标题翻译：模具及其制造方法
公开(公告)号：US08894892B2
公开(公告)日：2014-11-25
申请号：US13873814
申请日：2013-04-30
申请人： Fujikura Ltd.
发明人： Takaharu Hondo
IPC分类号： B29C59/16 , H05K3/00 , H05K3/10
CPC分类号： B29C59/16 , H05K3/0014 , H05K3/005 , H05K3/107 , H05K2203/0108
摘要： Providing a mold and a manufacturing method therefor wherein protrusions are easy to be pressed into a resin base material and the protrusions are easy to be pulled out from the resin base material. The present invention provides a mold comprising a stamping surface (1a) formed depending on a via pattern and a protruding portion (21, 22) formed in convex shape from the stamping surface (1a), wherein the protruding portion has a base portion (111, 121) merging into a main surface of the stamping surface (1a) to have a curvature and a slope portion (113, 123) progressively decreasing in outer diameter thereof from the base portion (111, 121) to a top portion (112, 122) of the protruding portion (21, 22).
摘要翻译：提供一种模具及其制造方法，其中突起容易被压入树脂基材中，并且突起容易从树脂基材拉出。本发明提供一种模具，其具有由通孔图案形成的冲压面（1a）和从冲压面（1a）形成为凸状的突出部（21,22），其中，突出部具有基部（111 ，121）合并到冲压表面（1a）的主表面以具有曲率，并且其外径从基部（111,121）逐渐减小到顶部（112,121）的倾斜部分（113,123） 122）突出部分（21,22）。

45. 发明申请

US20140313684A1 Non-Planar Printed Circuit Board with Embedded Electronic Components 有权
标题翻译：具有嵌入式电子元件的非平面印刷电路板
公开(公告)号：US20140313684A1
公开(公告)日：2014-10-23
申请号：US13864656
申请日：2013-04-17
申请人： United States of America as Represented by the Secretary of the Army
发明人： Bruce V. Hughes
IPC分类号： H05K1/11 , H05K3/10 , H05K1/18
CPC分类号： H05K3/107 , H05K1/0284 , H05K1/119 , H05K1/186 , H05K3/0014 , H05K3/10 , H05K3/4682 , H05K2201/056 , H05K2201/09018 , H05K2201/10583 , Y10T29/49155
摘要： A non-planar printed circuit board has an interior surface and an exterior surface. Between the interior surface and exterior surfaces are layers of conductive and dielectric materials. Passive and active electrical components are embedded within the interior and exterior surfaces. A hollow region is defined by the interior surface of the non-planar circuit board. The non-planar printed circuit board is manufactured on a mandrel having a non-planar shape such as, for example, a cylinder or sphere so as to form a hollow, curved non-planar structure.
摘要翻译：非平面印刷电路板具有内表面和外表面。在内表面和外表面之间是导电和介电材料层。被动和有源的电气部件嵌入在内部和外部表面。中空区域由非平面电路板的内表面限定。非平面印刷电路板在具有非平面形状的心轴上制造，例如圆柱体或球体，以便形成中空弯曲的非平面结构。

46. 发明申请

US20140264792A1 SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的封装和封装方法
公开(公告)号：US20140264792A1
公开(公告)日：2014-09-18
申请号：US14094763
申请日：2013-12-02
申请人： United Test and Assembly Center Ltd.
发明人： Yong Bo YANG , Chun Hong WO
IPC分类号： H01L21/768 , H01L23/495
CPC分类号： H01L23/562 , H01L21/4825 , H01L21/4828 , H01L21/4846 , H01L21/4853 , H01L21/563 , H01L21/565 , H01L21/76879 , H01L21/76885 , H01L23/142 , H01L23/147 , H01L23/3114 , H01L23/3128 , H01L23/3157 , H01L23/49503 , H01L23/49541 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5385 , H01L24/81 , H01L2021/60022 , H01L2224/10175 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/30505 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2224/81005 , H01L2924/15311 , H01L2924/19105 , H05K3/0023 , H05K3/0041 , H05K3/107 , H05K3/341 , H05K3/3452 , H05K3/4007 , H01L2924/00014 , H01L2924/00
摘要： Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die.
摘要翻译：提出了用于形成半导体封装的半导体封装和方法。该方法包括提供具有第一和第二主表面的封装衬底。封装衬底包括至少一个具有至少一个空腔的衬底层。互连结构形成。在空腔内形成至少一个导电柱，并且导电迹线和连接焊盘形成在封装衬底的第一主表面之上并且耦合到导电柱的顶表面。形成封装焊盘并且直接耦合到导电螺柱。提供了在其第一或第二表面上具有导电接触的裸片。管芯的导电触点电连接到互连结构。在封装基板上形成盖以封装模具。

47. 发明授权

US08835217B2 Device packaging with substrates having embedded lines and metal defined pads 有权
标题翻译：具有嵌入式线路和金属限定衬垫的衬底的器件封装
公开(公告)号：US08835217B2
公开(公告)日：2014-09-16
申请号：US12975934
申请日：2010-12-22
申请人： Mark S Hlad , Islam A Salama , Mihir K Roy , Tao Wu , Yueli Liu , Kyu Oh Lee
发明人： Mark S Hlad , Islam A Salama , Mihir K Roy , Tao Wu , Yueli Liu , Kyu Oh Lee
IPC分类号： H01L21/44 , H01L23/02
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/563 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49866 , H01L23/50 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/1112 , H01L2224/11462 , H01L2224/11464 , H01L2224/11466 , H01L2224/119 , H01L2224/13005 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1601 , H01L2224/16225 , H01L2224/16238 , H01L2224/165 , H01L2224/2919 , H01L2224/73204 , H01L2224/81121 , H01L2224/81191 , H01L2224/81444 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2224/831 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01103 , H01L2924/01108 , H01L2924/12042 , H01L2924/14 , H01L2924/15321 , H01L2924/2064 , H01L2924/37001 , H01L2924/3841 , H05K1/113 , H05K3/107 , H05K3/3436 , H05K3/421 , H01L2924/00014 , H01L2924/00
摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.
摘要翻译：封装衬底，能够减少凸起间距和封装组件。表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

48. 发明申请

US20140238725A1 METHOD OF FLATTENING SURFACE OF CONDUCTIVE STRUCTURE AND CONDUCTIVE STRUCTURE WITH FLATTENED SURFACE 审中-公开
标题翻译：导电结构表面和导向结构与平坦表面的方法
公开(公告)号：US20140238725A1
公开(公告)日：2014-08-28
申请号：US13778132
申请日：2013-02-27
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Erh-Hao Chen , Cha-Hsin Lin , Tzu-Kun Ku
IPC分类号： H05K1/02 , H05K3/26
CPC分类号： H05K3/107 , H05K3/045 , H05K3/247 , H05K2201/0376 , H05K2203/025
摘要： A method of flattening surface of conductive structure including a substrate, a dielectric layer on the substrate, and a conductive line formed in the dielectric layer is provided. A surface of the conductive line has a recess. A cover layer is formed on the substrate. A mechanical polishing process is performed to remove a portion of the cover layer. A remaining cover layer fills and levels the recess.
摘要翻译：提供了包括基板，基板上的电介质层和形成在电介质层中的导电线的导电结构的表面平坦化的方法。导线的表面具有凹部。在基板上形成覆盖层。执行机械抛光工艺以去除覆盖层的一部分。剩余的覆盖层填充并平整凹部。

49. 发明授权

US08800142B2 Package substrate unit and method for manufacturing package substrate unit 有权
标题翻译：封装衬底单元和用于制造封装衬底单元的方法
公开(公告)号：US08800142B2
公开(公告)日：2014-08-12
申请号：US12929680
申请日：2011-02-08
申请人： Hnin Nway San Nang , Kazuya Arai , Kei Fukui , Shinpei Ikegami , Yasuhito Takahashi , Hideaki Yoshimura , Hitoshi Suzuki
发明人： Hnin Nway San Nang , Kazuya Arai , Kei Fukui , Shinpei Ikegami , Yasuhito Takahashi , Hideaki Yoshimura , Hitoshi Suzuki
IPC分类号： H01K3/10 , H05K3/10
CPC分类号： H05K3/107 , B23K1/0016 , B23K3/0623 , B23K2101/42 , H01L23/49811 , H01L23/49822 , H01L2224/16225 , Y10T29/49165
摘要： A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.
摘要翻译：封装基板单元的半导体芯片安装层包括绝缘层，形成在绝缘层的顶表面上的导电种子金属层，形成在导电种子金属层的顶表面上的导电焊盘，基本上形成在金属柱导电焊盘的顶表面上的中心部分，以及形成为围绕导电焊盘和金属柱的阻焊层。

50. 发明申请

US20140218909A1 LIGHT SOURCE MODULE AND LIGHTING DEVICE HAVING THE SAME 有权
标题翻译：光源模块和具有相同功能的照明设备
公开(公告)号：US20140218909A1
公开(公告)日：2014-08-07
申请号：US14133822
申请日：2013-12-19
申请人： Samsung Electronics Co., Ltd.
发明人： Ariyoshi TETSUO , Cheon Ho PARK , Jong Pil WON , Ji Hoon YUN , Jun Ho JUNG
IPC分类号： F21K99/00 , H01L33/58 , H01L27/15
CPC分类号： F21K9/64 , F21K9/27 , F21K9/65 , F21K9/69 , F21V5/02 , F21V5/043 , F21Y2101/00 , F21Y2103/10 , F21Y2115/10 , H01L33/38 , H01L33/44 , H01L2224/13 , H01L2224/48091 , H05K1/021 , H05K1/0256 , H05K1/189 , H05K3/107 , H05K3/305 , H05K3/44 , H05K2201/0338 , H05K2201/0358 , H05K2201/0376 , H05K2201/09154 , H05K2201/098 , H05K2201/10106 , H05K2203/0139 , H05K2203/025 , H01L2924/00014
摘要： A light source module including a substrate, a plurality of light emitting devices installed on the substrate, and a plurality of lenses installed on the substrate to cover the plurality of light emitting devices, respectively, and each of the plurality of lenses having a pair of open end portions facing one another, the plurality of lenses arranged such that an open end portion of one lens faces an opened end portion of an adjacent lens is provided.
摘要翻译：一种光源模块，包括基板，安装在基板上的多个发光装置，以及分别安装在基板上以覆盖多个发光装置的多个透镜，并且多个透镜中的每一个具有一对所述多个透镜被设置为使得一个透镜的开口端部面向相邻透镜的开口端部。

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