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41. 发明授权

US3225315A Differential code modulator 失效
标题翻译：差分码调制器
公开(公告)号：US3225315A
公开(公告)日：1965-12-21
申请号：US29321663
申请日：1963-07-05
申请人： JOHANN HOLZER
发明人： JOHANN HOLZER
IPC分类号： H03M3/02
CPC分类号： H03M3/02

42. 发明授权

US3112369A Telecommunication system 失效
标题翻译：电信系统
公开(公告)号：US3112369A
公开(公告)日：1963-11-26
申请号：US2215360
申请日：1960-04-14
申请人： ERICSSON TELEFON AB L M
发明人： WILLIAM SPARRENDAHL GUNNAR ERI
IPC分类号： H03M3/02 , H04J3/17 , H04M1/00 , H04M1/50 , H04Q11/04
CPC分类号： H04Q11/04 , H03M3/02 , H04J3/17 , H04M1/00 , H04M1/50

43. 发明授权

US2990520A Delta modulation system 失效
标题翻译：增量调制系统
公开(公告)号：US2990520A
公开(公告)日：1961-06-27
申请号：US85421259
申请日：1959-11-19
申请人： COURCHENE JR ERNEST E , JOHANN HOLZER
发明人： COURCHENE JR ERNEST E , JOHANN HOLZER
IPC分类号： H03M3/02
CPC分类号： H03M3/02

44. 发明授权

US2629857A Communication system utilizing constant amplitude pulses of opposite polarities 失效
标题翻译：利用具有相反极性的恒定幅度脉冲的通信系统
公开(公告)号：US2629857A
公开(公告)日：1953-02-24
申请号：US77866247
申请日：1947-10-08
申请人： INT STANDARD ELECTRIC CORP
发明人： MAURICE DELORAINE EDMOND , BORIS DERJAVITCH
IPC分类号： H03M3/02
CPC分类号： H03M3/02

45. 发明申请

US20180205352A1 AMPLIFIERS WITH DELTA-SIGMA MODULATORS USING PULSE-DENSITY MODULATIONS AND RELATED PROCESSES 审中-公开
公开(公告)号：US20180205352A1
公开(公告)日：2018-07-19
申请号：US15873532
申请日：2018-01-17
申请人： KAPIK INC.
发明人： Robert Neil McKENZIE , William Martin SNELGROVE , Wai Tung NG
IPC分类号： H03F3/217 , H03F1/06 , H03F3/24 , H03L7/081 , H03M3/02 , H03M7/30 , H04B14/06 , H04L27/36 , G06F7/60
CPC分类号： H03F3/2171 , G06F7/602 , H03F1/06 , H03F3/185 , H03F3/2173 , H03F3/24 , H03F2200/03 , H03F2200/331 , H03L7/0816 , H03M3/02 , H03M3/502 , H03M7/3011 , H03M7/3015 , H04B14/062 , H04L27/36
摘要： An audio amplifier system includes a delta-sigma modulator configured to receive an m-bit digital audio input signal and to generate a pulse density modulated signal based on the m-bit digital audio input signal. An analog power stage is coupled to the delta-sigma modulator to receive the pulse density modulated signal and amplify the pulse density modulated signal to generate an amplified pulse density modulated signal. A feedback circuit is coupled to the delta-sigma modulator and the analog power stage. The feedback circuit is configured to receive the amplified pulse density modulated signal and the pulse density modulated signal and to determine a digital error signal representative of a difference between the amplified pulse density modulated signal and the pulse density modulated signal. The feedback circuit is further configured to provide the digital error signal to the delta-sigma modulator for applying the digital error signal to a representation of the m-bit digital audio input signal.

46. 发明申请

US20170201236A1 DIGITAL FILTER 有权
公开(公告)号：US20170201236A1
公开(公告)日：2017-07-13
申请号：US15316807
申请日：2015-05-15
申请人： Azbil Corporation
发明人： Tetsuya KAJITA
IPC分类号： H03H17/02
CPC分类号： H03H17/025 , H03H17/0282 , H03H17/0286 , H03H17/0671 , H03M3/02 , H03M3/462
摘要： A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.

47. 发明申请

US20170134055A1 SIGNAL AMPLIFICATION AND TRANSMISSION BASED ON COMPLEX DELTA SIGMA MODULATOR 审中-公开
公开(公告)号：US20170134055A1
公开(公告)日：2017-05-11
申请号：US15318067
申请日：2014-06-23
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Mojtaba Ebrahimi , Mohamed Helaoui , Fadhel Ghannouchi , Fahimi Elsayed , Bradley John Morris
IPC分类号： H04B1/04 , H04L27/26 , H03F3/24 , H03M7/30 , H03F3/19
CPC分类号： H04B1/0475 , H03F3/19 , H03F3/245 , H03F2200/331 , H03F2200/451 , H03M3/02 , H03M3/40 , H03M7/3015 , H03M7/302 , H04L27/2614
摘要： Apparatuses and methods for power amplification and signal transmission using complex delta-sigma modulation are disclosed. In one embodiment, a complex delta sigma modulator unit comprising a complex polar quantizer within an integrator loop is disclosed. The complex polar quantizer quantizes the envelope of a complex integrated signal and produces a complex quantized output signal of substantially constant envelope. The complex quantized output signal is used in deriving a complex feedback signal within the integrator loop of the complex DSM. The complex quantized output signal may be used in driving a power amplifier substantially at saturation. In some embodiments, an adjacent channel power ratio (ACPR) enhancement technique is used to reduce the quantization noise in the complex quantized output signal.

48. 发明申请

US20160373241A1 PHASE DETECTION IN AN ANALOG CLOCK DATA RECOVERY CIRCUIT WITH DECISION FEEDBACK EQUALIZATION 有权
标题翻译：具有决策反馈均衡的模拟时钟数据恢复电路中的相位检测
公开(公告)号：US20160373241A1
公开(公告)日：2016-12-22
申请号：US14743870
申请日：2015-06-18
申请人： ALTERA CORPORATION
发明人： Wenyi JIN , Jihong REN , Hae-Chang LEE
IPC分类号： H04L7/00 , H04L25/03
CPC分类号： H04L7/0058 , H03M3/02 , H04L7/0087 , H04L7/033 , H04L25/03057 , H04L25/03885
摘要： An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.
摘要翻译：本发明的实施例涉及一种具有判决反馈均衡的接收机电路中的相位检测方法。产生部分均衡和全均衡边缘信号。来自判决反馈均衡器的第一抽头的反馈与剩余的多个抽头的反馈分离。来自多个抽头（不包括第一抽头）的反馈用于产生部分均衡边沿信号，而来自所有抽头的反馈被用于产生全均衡边缘信号。部分均衡和全均衡边缘信号由相位检测电路用于提供高精度的数据采样位置，以提高性能。

49. 发明授权

US09112522B2 Delta conversion analog to digital converter providing direct and quadrature output 有权
标题翻译： Delta转换模数转换器提供直接和正交输出
公开(公告)号：US09112522B2
公开(公告)日：2015-08-18
申请号：US14319154
申请日：2014-06-30
申请人： Enphase Energy, Inc.
发明人： Michael Harrison
IPC分类号： H03M3/00 , H03M3/02
CPC分类号： H03M3/02 , H03M3/40
摘要： Embodiments of the present invention are directed to an analog to digital converter, comprising a comparator for comparing an analog input signal and an analog feedback signal output from a digital to analog converter to generate a digital direct output signal, a summer, coupled to the comparator, for summing the digital output signal with a digital feedback signal to generate a summed signal, a first integrator, coupled to the summer, for integrating the summed signal to generate a direct output signal and a second integrator, coupled to the first integrator and to the summer, for integrating the direct output signal to generate the digital feedback signal as a quadrature output signal.
摘要翻译：本发明的实施例涉及一种模数转换器，包括比较器，用于比较模拟输入信号和从数模转换器输出的模拟反馈信号，以产生耦合到比较器的数字直接输出信号，加法器用于将数字输出信号与数字反馈信号相加以产生加法信号，耦合到加法器的第一积分器，用于积分加和信号以产生直接输出信号和第二积分器，耦合到第一积分器，并耦合到第一积分器，用于积分直接输出信号以产生数字反馈信号作为正交输出信号。

50. 发明申请

US20150222760A1 METHOD AND APPARATUS FOR PROVIDING RINGING TIMEOUT DISCONNECT SUPERVISION IN REMOTE TELEPHONE EXTENSIONS USING VOICE OVER PACKET-DATA-NETWORK SYSTEMS (VOPS) 审中-公开
标题翻译：使用分组数据网络系统（VOPS）中的语音来提供远程电话扩展中的振铃超时断开监控的方法和装置
公开(公告)号：US20150222760A1
公开(公告)日：2015-08-06
申请号：US14500429
申请日：2014-09-29
申请人： Cisco Technology, Inc.
发明人： Wing-Kuen Chung , Cherng-Daw Hwang , Michael Edric Tasker
IPC分类号： H04M19/02 , H04M7/00 , H04M3/02 , H04L12/66
CPC分类号： H04M19/026 , H03M3/02 , H04L12/4633 , H04L12/66 , H04M3/02 , H04M7/0024 , H04M7/006
摘要： A Multiservice Access Concentrator (MAC) provides a time limit for a first ringing voltage signal in response to an attempted call. The call is attempted via a voice over packet-data-network system (VOPS), wherein the VOPS comprises voice over Internet Protocol (IP), voice over Frame Relay, voice over Asynchronous Transfer Mode (ATM), and voice over High-level Data Link Control (HDLC) network systems. Generation of the first ringing voltage signal is terminated upon expiration of the time limit. A control message is transmitted to terminate the attempted call, wherein the control message is transmitted via the VOPS.
摘要翻译：响应于尝试的呼叫，多业务接入集中器（MAC）为第一振铃电压信号提供时间限制。通过分组数据网络系统（VOPS）上的语音尝试呼叫，其中VOPS包括基于因特网协议（IP）的语音，帧中继上的语音，异步传输模式（ATM）上的语音和高级语音数据链路控制（HDLC）网络系统。第一振铃电压信号的产生在期限到期时终止。发送控制消息以终止尝试的呼叫，其中通过VOPS发送控制消息。

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